MOS Capacitor Merged Transistor Neutralization
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Solution Overview
Problem
Conventional transconductance circuits face challenges in compensating for the Miller effect at high frequencies, particularly in millimeter wave or terahertz applications, due to parasitic inductance introduced in interconnects, which affects neutralization and reduces gain and bandwidth.
Innovation Solution
A differential pair of compensated transistors with a back-gate region and a metallization layer that couples the gates and back-gates of MOS transistors together, forming a transconductance circuit with alternating source and drain regions and integrated MOS capacitors to match the size and track gate-drain capacitances effectively, reducing parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional neutralization capacitance layout is used, then gate-drain capacitance compensation is achieved, but parasitic inductance increases at high frequencies
Solution Approach 1:
The patent merges the neutralization capacitance function directly into the transistor structure by using the substrate as a common back-gate for multiple transistors. This integration eliminates separate interconnect paths that would introduce parasitic inductance, while maintaining the capacitance compensation function through the shared substrate connection.
Solution Approach 2:
The patent transitions from planar interconnect-based neutralization to a vertical/substrate-based neutralization approach. By utilizing the substrate dimension as a common back-gate region, the design eliminates the need for surface-level interconnects that introduce parasitic inductance, effectively moving the neutralization function to a different spatial dimension.
2Measurement precision
If MOS capacitors are used for neutralization, then gate-drain capacitance tracking is improved, but device area increases
Solution Approach 1:
The substrate serves multiple functions simultaneously: it acts as the common back-gate for neutralization, provides the foundation for transistor operation, and enables capacitance tracking through its inherent electrical properties. This multi-functionality eliminates the need for separate MOS capacitor structures, reducing overall device area while maintaining tracking accuracy.
Solution Approach 2:
The substrate inherently provides the neutralization function through its electrical characteristics and connection to transistor back-gates. The substrate's natural capacitance and conductivity properties are utilized to achieve gate-drain capacitance tracking without requiring additional dedicated capacitor components, allowing the structure to serve itself for neutralization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances linearity and compensates for the Miller effect at high frequencies, improving gain and bandwidth by minimizing parasitic inductance and accurately tracking gate-drain capacitances, thus addressing the limitations of conventional circuits in millimeter wave and terahertz applications.
Implementation Method 1
A metal layer is provided that couples the back-gates together. The metal layer reduces inductance associated with an interconnect
Implementation Method 2
MOS capacitors Q3 and Q4 are cross-coupled between the transistors Q1 and Q2 to provide capacitances to counter the gate-drain capacitances of transistors Q1 and Q2
Data Source
AI summary
Neutralization capacitances are commonly employed to compensate for the Miller effect; however, at higher frequencies, the parasitic inductance introduced in the interconnect can affect the neutralization. Here, a layout has been provided where a MOS capacitor is merged with a complementary transistor. By having this merged device, the layout is compact and reduces interconnect area, which reduces the effects of parasitic inductance at higher frequencies (i.e., millimeter wave or terahertz). This layout can also be used to implement linearity enhancement schemes.