MOS Capacitor Mesh Gate Structure for High Capacitance

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Solution Overview

Problem

Existing MOS capacitors face challenges in enhancing capacitance without increasing area and preventing characteristic degradation due to leakage currents, particularly in semiconductor devices like image sensors.

Innovation Solution

The design includes a MOS capacitor with a mesh-type gate structure, an isolation layer defining an active region, and strategically positioned impurity regions and plugs to increase capacitance while preventing leakage currents, using a gate dielectric layer and spacers to enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the area of MOS capacitor is increased to enhance capacitance, then capacitance is improved, but device area increases

Engineering Contradiction:

ImprovecapacitanceVSAvoiddevice area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The gate electrode is divided into multiple gate patterns (first gate patterns and second gate patterns) arranged in an interlaced manner, creating multiple gate regions within a compact area. This segmentation increases the effective gate area and thus capacitance without proportionally increasing the overall device footprint

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The gate patterns are arranged in two dimensions with first gate patterns extending in a first direction and second gate patterns extending in a second direction intersecting the first direction. This two-dimensional interlaced arrangement maximizes the use of available space, increasing capacitance while maintaining a compact device area

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If impurity region is positioned close to isolation layer to reduce area, then device area is reduced, but leakage current increases causing characteristic degradation

Engineering Contradiction:

Improvedevice areaVSAvoidcharacteristic stability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The impurity region is selectively positioned to be spaced from the isolation layer only in specific local areas where leakage current paths exist, while maintaining close proximity in other areas to minimize device footprint. This localized adjustment prevents leakage current without unnecessarily increasing overall device area

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves capacitance without area expansion and mitigates leakage current issues, enhancing the performance of MOS capacitors in semiconductor devices like image sensors.

Implementation Method 1

a gate dielectric layer positioned between the gate and the impurity region

Methodology Applied

Scientific EffectDielectric isolation: Dielectric

Implementation Method 2

a gate having a plurality of gate patterns adjacent to each other with a gap therebetween

Methodology Applied

Scientific EffectCapacitance enhancement through increased surface area: Capacitance

Data Source

PatentUS10381492B2MOS capacitor and image sensor having the same

Publication Date: 2019.08.13 SK HYNIX INC

AI summary

A MOS capacitor may include: an isolation layer formed in a substrate and defining an active region; a first electrode formed in the active region, and including an impurity region spaced from the isolation layer; and a second electrode formed over the substrate overlapping the impurity region, and including a gate having a plurality of gate patterns adjacent to each other with a gap therebetween.