MOS Capacitor Parallel pMOS nMOS Linearity
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Solution Overview
Problem
Conventional MOS capacitors exhibit poor capacitance linearity over voltage ranges, making them unsuitable for applications requiring high linearity.
Innovation Solution
A MOS capacitor design where a p-type MOS transistor and an n-type MOS transistor are electrically connected in parallel, with a deep n-type well encompassing both transistors to enhance capacitance linearity and operational voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional MOS capacitor is used, then the area occupied is minimized, but the capacitance linearity deteriorates
Solution Approach 1:
The patent combines a p-type MOS transistor and an n-type MOS transistor into a single capacitor structure, where both transistors share common source and drain regions. This merging approach achieves improved capacitance linearity by utilizing the complementary characteristics of pMOS and nMOS devices while maintaining a compact integrated structure that does not significantly increase area occupation.
Solution Approach 2:
The invention segments the capacitor functionality into two distinct transistor components (pMOS and nMOS) that operate in parallel. Each transistor contributes differently to the overall capacitance characteristics across the voltage range, with pMOS dominating at negative voltages and nMOS at positive voltages, thereby achieving superior linearity through functional segmentation.
2Adaptability or versatility
If a single-type MOS capacitor is used, then the device structure is simple, but the operational voltage range is limited
Solution Approach 1:
The patent creates a universal capacitor structure that can operate effectively across both negative and positive voltage ranges by integrating both p-type and n-type MOS transistors. This multi-functional design allows the single capacitor to adapt to different voltage conditions, with each transistor type optimizing performance in its respective voltage polarity range, thereby expanding the overall operational versatility.
Data Source
AI summary
A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.