Self-Biased MOS Cascode Input Pair for Low-Headroom Gain
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Solution Overview
Problem
Existing cascode differential input pairs in operational transconductance amplifiers face limitations in voltage gain due to high power consumption, larger die area requirements, and reduced input common mode voltage range, necessitating additional bias generation branches and fixed drain voltages that limit their performance.
Innovation Solution
A cascode differential input pair design utilizing intrinsic common-gate transistors and regular common-source transistors, where the sources of the common-source transistors are connected at a common node, allowing self-biasing without additional branches, and maintaining transistors in saturation regions with reduced headroom voltage and increased output impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional bias generation branches are used to provide gate voltage for common-gate transistors, then the cascode differential input pair can operate with higher output resistance and voltage gain, but the die area and power consumption increase
Solution Approach 1:
The patent combines the bias generation function with the existing common-source transistor structure by connecting the gate of the common-gate transistor to the source of the common-source transistor. This merging eliminates the need for separate bias generation branches while maintaining the required gate voltage for common-gate transistor operation, thereby reducing die area without compromising voltage gain.
Solution Approach 2:
The source node of the common-source transistor serves multiple functions: it acts as the current source connection point and simultaneously provides the gate bias voltage for the common-gate transistor. This multi-functionality eliminates redundant circuit elements and reduces overall circuit complexity while maintaining performance.
2Reliability
If additional bias generation branches are used to provide gate voltage for common-gate transistors, then the cascode differential input pair can operate with higher output resistance and voltage gain, but the power consumption increases
Solution Approach 1:
The patent merges the bias generation function into the existing transistor structure, eliminating separate bias branches that would consume additional power. The gate bias for common-gate transistors is derived from the source voltage of common-source transistors, requiring no additional power-consuming bias circuits.
Solution Approach 2:
The circuit generates its own bias voltage internally through the source node of the common-source transistors, which automatically provides the required gate voltage for common-gate transistors. This self-service mechanism eliminates the need for external power-consuming bias generation circuits.
3Reliability
If fixed drain voltage is used based on gate voltage from additional branch, then the common-gate transistors can be properly biased, but the input common mode voltage range is reduced
Solution Approach 1:
The patent makes the drain voltage dynamic by connecting it to the gate voltage of the common-source transistor instead of using a fixed bias voltage. As the common mode input voltage varies, the gate voltage of the common-source transistor varies accordingly, which in turn dynamically adjusts the drain voltage to maintain proper biasing conditions across the entire input common mode voltage range.
Solution Approach 2:
The circuit implements feedback by connecting the gate of the common-gate transistor to the source of the common-source transistor, which is controlled by the gate voltage. This feedback mechanism automatically adjusts the bias conditions to maintain transistor saturation across varying input common mode voltages, expanding the usable voltage range.
4Reliability
If conventional cascode structure with separate bias branches is used, then higher output resistance is achieved, but the headroom voltage requirement increases
Solution Approach 1:
The patent merges the bias generation function with the transistor structure, eliminating the voltage drop across separate bias branches. By directly connecting the gate of the common-gate transistor to the source of the common-source transistor, the circuit achieves the necessary biasing with minimal voltage overhead, reducing headroom requirements while maintaining high output resistance.
Data Source
AI summary
Methods and devices for a cascode differential input pair with low headroom voltage and high output impedance are presented. The cascode differential input pair includes first and second input (cascode) stages, each including a common-source regular transistor in series connection with a common-gate intrinsic transistor. Sources of the regular transistors are tied, and gates of the intrinsic transistors are tied. A gate voltage to the intrinsic transistors is provided by a source voltage at the sources of the regular transistors, the source voltage based on a common mode input voltage of the cascode differential input pair. According to one aspect, the cascode differential input pair is part of a differential amplifier that includes a current source coupled to the sources of the regular transistors, and a load coupled to drains of the intrinsic transistors.