MOS Standard Cells With Electrically Coupled Source Regions
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Solution Overview
Problem
Conventional MOS standard cells face challenges in maintaining the required source-drain tip-to-tip spacing as they are vertically scaled, leading to potential erroneous operation due to reduced space for transistor elements, which affects the design rules and overall area efficiency.
Innovation Solution
The implementation of electrically coupled source regions and supply rails in MOS standard cells, where the source region is formed adjacent to a plane between the supply rail, allowing for a minimum required source-drain tip-to-tip distance without overlapping, thus enabling reduced area consumption while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If supply rails are vertically scaled to reduce rail width, then overall area of MOS standard cell is reduced, but source-drain tip-to-tip spacing cannot be maintained
Solution Approach 1:
The source region is positioned adjacent to a plane in the X-Z axis direction rather than overlapping vertically with the supply rail in the Z-axis direction. This dimensional repositioning allows the source region to be electrically coupled to the supply rail while maintaining horizontal spacing from adjacent drain regions, thus preserving source-drain tip-to-tip distance even with reduced rail width
Solution Approach 2:
The plane in the X-Z axis direction acts as an intermediary reference that separates the source region from the supply rail in the vertical Z-axis direction. This intermediary positioning enables the source region to be electrically coupled to the supply rail through the plane interface while maintaining the required horizontal spacing from adjacent cell drain regions
2Productivity
If technology node size is scaled down, then number of device elements per area increases, but spacing between transistor elements becomes insufficient
Solution Approach 1:
By repositioning the source region from a vertical overlap configuration to a horizontal adjacent configuration relative to the supply rail, the design achieves better utilization of horizontal spacing. This allows smaller technology nodes to be packed more densely while maintaining the required source-drain tip-to-tip spacing through the intermediary plane separation
Data Source
AI summary
Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells are disclosed. In one aspect, a MOS standard cell includes supply rails disposed in a first metal layer and along respective axes in an X-axis direction. The MOS standard cell includes metal lines disposed in the first metal layer and along respective axes in the X-axis direction. The MOS standard cell includes a source region formed in a semiconductor substrate beneath the first metal layer and adjacent to a plane in an X-Z-axis direction disposed between a supply rail and the source region. The source region is electrically coupled to the corresponding supply rail. Forming the source region in this manner allows the MOS standard cell to be disposed adjacent to other MOS standard cells while achieving the minimum required source-drain tip-to-tip spacing.