MOS Transistor Channel Optimization via Crystal Plane Orientation
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Solution Overview
Problem
Existing semiconductor devices with narrow channel width MOS transistors face limitations in improving electric characteristics due to higher threshold voltages, which hinder the enhancement of current drivability and switching performance.
Innovation Solution
The semiconductor device incorporates a device isolation layer defining active regions with inclined edge surfaces and a semiconductor pattern with a flat top surface of a (100) crystal plane, overlapped by a gate pattern including a lanthanum-based gate insulating layer, and utilizes selective epitaxial growth for silicon and silicon-germanium patterns to optimize channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a layer containing lanthanum is formed in NMOS transistors having narrow channel width, then threshold voltage reduction is achieved for wide channel transistors, but threshold voltage becomes higher than expected for narrow channel width transistors
Solution Approach 1:
The patent applies local quality by providing different crystal plane orientations at different locations within the channel region. The channel region includes a first region with a first crystal plane orientation and a second region with a second crystal plane orientation different from the first. This allows different portions of the channel to have different electrical characteristics, enabling threshold voltage control that is effective for narrow channel width transistors while maintaining the benefits of lanthanum layer formation.
2Productivity
If channel width is reduced to improve current drivability, then switching performance is enhanced, but threshold voltage increases due to narrow channel width effect
Solution Approach 1:
By creating regions with different crystal plane orientations within the channel, the patent locally modifies electrical properties to counteract the narrow channel width effect. The first region and second region with different orientations provide complementary characteristics that stabilize threshold voltage while maintaining high current drivability in narrow channel devices.
Solution Approach 2:
The channel region functions as a composite structure with different crystal plane orientations coexisting in the same transistor channel. This composite approach combines the advantages of different crystal orientations to achieve both low threshold voltage and high current drivability, resolving the contradiction between these two performance parameters.
3Manufacturing precision
If photolithography resolution limit is used to define minimum feature size, then manufacturing precision is constrained, but device performance is limited by resulting narrow channel width
Solution Approach 1:
The patent overcomes photolithography resolution limits by using crystal plane orientation variations rather than purely dimensional scaling. By controlling the crystal structure at different locations in the channel region, the invention achieves enhanced electric characteristics without requiring further reduction of minimum feature size defined by photolithography constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains low threshold voltages for NMOS transistors while reducing channel width, enhancing current drivability and switching speed, and also reduces threshold voltage for PMOS transistors by using a silicon-germanium pattern with lower band gap energy.
Implementation Method 1
utilizes selective epitaxial growth for silicon and silicon-germanium patterns to optimize channel regions
Data Source
AI summary
A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.