Gate Current Compensation in MOS Current Mirror Circuits
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Solution Overview
Problem
Current mirror circuits face challenges in accurately copying currents due to significant gate currents, especially in miniaturized transistors where parasitic currents lead to output current losses, exacerbated by the tunneling effect in thin gate oxide layers.
Innovation Solution
The implementation of a current mirror circuit using P-type MOS transistors with a diode-connected configuration, along with additional circuits to isolate and compensate for gate currents, and the use of transistors with double oxide layers to minimize parasitic currents, ensuring accurate current duplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If miniaturized transistors are used in current mirror circuits, then device size is reduced, but gate current increases due to tunneling effect in thin gate oxide layers
Solution Approach 1:
The patent extracts and isolates the harmful gate current from the main current mirror operation by introducing a dedicated isolation circuit. This circuit separates the gate current path from the signal path, allowing the gate current to be measured and compensated without affecting the primary current copying function. The extraction principle enables the system to handle the harmful effect independently while maintaining miniaturization benefits.
Solution Approach 2:
The patent changes the electrical parameters of the transistor by introducing compensation currents that adjust the effective gate current. Through parameter modification, the system compensates for the increased gate current caused by miniaturization and thin oxide layers, restoring the current mirror accuracy without increasing device dimensions.
2Device complexity
If gate current is not compensated, then circuit complexity is low, but output current accuracy deteriorates due to parasitic currents
Solution Approach 1:
The patent implements a feedback mechanism where the gate current is continuously monitored and used to generate a compensation current. This feedback loop adjusts the output current dynamically to account for parasitic effects, ensuring high copying accuracy. The feedback principle transforms a static circuit into an adaptive system that automatically corrects for accuracy degradation.
Solution Approach 2:
The patent introduces an intermediary compensation circuit that acts as a mediator between the gate current source and the output current. This intermediary component processes the gate current information and generates appropriate compensation signals, enabling accurate current copying without directly modifying the core current mirror structure.
3Measurement precision
If additional compensation circuits are added, then current copying accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the compensation function with the existing current mirror structure by integrating isolation and compensation circuits that share common components and nodes. This merging approach enables accuracy improvement without proportionally increasing device complexity, as the compensation mechanisms are embedded within the overall circuit architecture rather than added as separate independent blocks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of current copying by accounting for and mitigating parasitic currents, thereby reducing losses and improving the performance of current mirror circuits, especially in miniaturized transistor designs.
Implementation Method 1
parasitic currents lead to output current losses, exacerbated by the tunneling effect in thin gate oxide layers
Data Source
AI summary
In an embodiment an electronic device includes a first MOS-type transistor and a second MOS-type transistor connected as current mirrors, wherein the first transistor is diode connected and a first circuit configured to provide a first current equal to a first gate current of the first transistor multiplied by a size ratio of the first and second transistors.