MOS Current Mirror Gate Coupling for Faster Current Copying
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Solution Overview
Problem
Existing current copying devices, such as current mirrors with MOS transistors, experience delays in modifying the output current in response to changes in the input current, especially when charging or discharging capacitive elements.
Innovation Solution
The proposed device includes a first resistor connected to the input node, a MOS transistor with its source connected to a supply voltage node, and a capacitor coupling the input node to the transistor's gate, along with a biasing circuit providing a biasing voltage to the transistor's gate through a second resistor, allowing for faster transmission of current modifications across the MOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a current mirror with MOS transistors is used to copy current, then the output current is determined by the input current, but a delay occurs when modifying the output current in response to changes in the input current
Solution Approach 1:
The patent introduces a capacitor as an intermediary element connected between the input node and the gate of the MOS transistor. This capacitor mediates the signal transmission by providing a direct capacitive coupling path that bypasses the conventional resistive path, thereby accelerating the response of the gate voltage to input current changes and reducing the delay in output current modification.
Solution Approach 2:
The patent modifies the static biasing network by adding a capacitor that enables dynamic response. The capacitor allows the gate voltage to change dynamically in response to input current variations, transforming the otherwise static biasing condition into a dynamic system that can quickly track input current changes, thus improving the speed of current copying.
2Productivity
If the output current is used for charging or discharging a capacitive element, then the current copying function is achieved, but the delay in current modification limits the charging/discharging speed
Solution Approach 1:
The capacitor connected to the gate acts as an intermediary that directly couples the input current changes to the gate voltage, enabling faster charging/discharging of the capacitive load. This capacitive coupling path allows the gate to respond more quickly to input changes, thereby increasing the productivity of the current copying function when driving capacitive loads.
3Speed
If the delay between input and output current modification is reduced, then the slew rate and bandwidth are enhanced, but additional circuit elements may increase device complexity
Solution Approach 1:
The patent uses a capacitor as a simple intermediary element that provides significant performance improvement with minimal added complexity. The capacitor is a basic passive component that can be easily integrated into the existing current mirror structure, enhancing slew rate and bandwidth without requiring complex active circuits or multiple additional transistors.
Solution Approach 2:
The patent changes the electrical parameters of the gate biasing network by adding capacitive coupling, which fundamentally alters the frequency response and transient behavior of the circuit. This parameter change enables higher slew rate and bandwidth while maintaining a relatively simple circuit topology, as the capacitor modifies the existing biasing path rather than requiring a complete circuit redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the delay between input and output current modifications, enhancing the slew rate and bandwidth of the amplifier while maintaining low power consumption and surface area, allowing for faster charging or discharging of capacitive loads.
Implementation Method 1
a first capacitor connected between the input node and the gate of the first MOS transistor
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present disclosure relates to a device (1041; 1061) comprising an input node (1041i; 1061i) receiving a first current (11; 12), an output node (1041o; 1061o) providing a second current (13; 14), a first resistor (RA) connected between the input node and a first node (108) receiving a supply voltage (VSS), a MOS transistor (M2) having a source connected to the first node (108) and a drain coupled to the output node (1041o; 1061o), a second resistor (RS) having a first terminal connected to a gate of the MOS transistor (M2), a biasing circuit (200) providing a biasing voltage on a second terminal of the second resistor (RS), and a capacitor (C) connected between the input node (1041i; 1061i) and the gate of the MOS transistor (M2).