MOS Current Mirror Gate-Length Tuning for Rational Current Scaling
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Solution Overview
Problem
Current mirror circuits lack the capability to efficiently multiply a current by a rational number, limiting their performance in electronic devices.
Innovation Solution
A current mirror circuit comprising MOS-type transistors with varying gate lengths, where the gate lengths of the transistors are the product of a reference gate length and rational coefficients, allowing for the series coupling of multiple transistors to achieve the desired current multiplication, with adjustable coefficients to fine-tune the output current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional current mirror circuits use transistors with identical gate lengths, then the circuit structure is simple, but the capability to multiply current by a rational number is limited
Solution Approach 1:
The patent divides the current mirror function into multiple transistors with different gate lengths (L1, L2, L3) instead of using a single transistor. Each transistor segment contributes to achieving the overall current multiplication ratio, enabling rational number multiplication while maintaining modular structure
Solution Approach 2:
The patent applies different gate lengths to different transistors within the same current mirror circuit to achieve specific current multiplication ratios. Each transistor is locally optimized with a specific gate length (L1, L2, or L3) to contribute to the overall rational multiplication factor, rather than using uniform gate lengths throughout
2Measurement precision
If MOS transistors with different gate lengths are used to achieve current multiplication, then precise current control is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the gate length parameter (L1, L2, L3) of MOS transistors to achieve different current multiplication ratios. By systematically varying this single parameter while keeping other parameters constant, the circuit achieves precise current control with simplified design and reduced sensitivity to manufacturing variations
Data Source
AI summary
A current mirror circuit includes a first MOS-type transistor and a second MOS-type transistor assembled as a current mirror, wherein the first transistor has a first gate length different from a second gate length of the second transistor.