MOS Decoupling Capacitor With Segmented Gate Lengths
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Solution Overview
Problem
In semiconductor integrated circuit devices, the miniaturization of transistors leads to thinner gate oxidized films, increasing the risk of electrostatic discharge (ESD) damage and interfering with the charge and discharge of decoupling capacitors due to increased on-resistance, which destabilizes power supply noise reduction.
Innovation Solution
A decoupling capacitor design utilizing MOS transistors with varying gate lengths to function as either resistor or capacitor elements, where P-channel and N-channel transistors are arranged in series between power supply wirings, with specific gate lengths to manage capacitance and resistance, and dummy wires are used to suppress changes in adjacent logic cell properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the transistor size is enlarged in the channel length direction to increase capacitance, then the capacitance of the decoupling capacitor is increased, but the on-resistance between source and drain increases, interfering with charge and discharge
Solution Approach 1:
The decoupling capacitor is segmented into multiple capacitor elements connected in parallel, each with its own transistor. This allows the total capacitance to be increased by adding more segments rather than enlarging a single transistor's channel length, thereby avoiding the on-resistance penalty.
Solution Approach 2:
Different transistors are assigned different gate lengths optimized for their specific functions: some transistors have shorter gate lengths to minimize on-resistance for efficient charge/discharge, while the overall parallel configuration provides the required total capacitance. Each local element has optimized properties for its role.
2Productivity
If the gate oxidized film is made thinner due to transistor miniaturization, then the transistor size is reduced, but the risk of electrostatic discharge (ESD) damage increases
Solution Approach 1:
A protection circuit is introduced as an intermediary element between the thin gate oxidized film and the ESD threat. This protection circuit acts as a mediator that intercepts and safely dissipates ESD energy before it can damage the delicate gate oxide, enabling continued use of miniaturized transistors with thinner gate films.
Solution Approach 2:
The protection circuit provides beforehand cushioning against ESD damage by being positioned to catch and absorb electrostatic discharge events before they reach the vulnerable thin gate oxidized film. This preventive measure cushions the delicate transistor structure from harmful external factors.
3Reliability
If the on-resistance is reduced to improve charge and discharge efficiency, then the transistor channel length is shortened, but the capacitance decreases
Solution Approach 1:
Multiple capacitor elements with short-channel transistors (low on-resistance) are merged by connecting them in parallel. The individual low on-resistance transistors maintain efficient charge/discharge, while their parallel combination provides the required total capacitance that a single long-channel transistor would provide.
Solution Approach 2:
Instead of increasing capacitance by extending the channel length in one dimension (which increases resistance), the solution moves to another dimension by adding more parallel transistor elements. The capacitance is increased through multiplication of parallel elements rather than enlargement of individual element dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances ESD resistance and prevents direct high-potential application to transistor gates, maintaining efficient charge and discharge during power supply voltage fluctuations while minimizing manufacturing variations and transistor property changes.
Implementation Method 1
a gate oxidized film is formed to form a capacitor element
Implementation Method 2
the possibility of the occurrence of electrostatic discharge (ESD) damage
Data Source
AI summary
A decoupling capacitor includes a first MOS transistor having a first conductivity type. The first MOS transistor functions as a resistor element due to an on-resistance between its source and drain. The source is connected to first power supply wiring. The decoupling capacity further includes a second MOS transistor having a second conductivity type. The second MOS transistor is connected to second power supply wiring. The second MOS transistor functions as a capacitor element and has a gate length greater than that of the first MOS transistor.