MOS Delay Circuit Topology for Long Delay in Less Area
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Solution Overview
Problem
Conventional delay circuits require larger capacitance values for longer delay times, leading to increased circuit size, which is inefficient and impractical for compact designs.
Innovation Solution
A delay circuit design utilizing MOS transistors of alternating conductivity types and a capacitor, along with additional components like constant current sources and resistors, to generate the same delay time with a more compact size, allowing for reduced capacitance and circuit size without sacrificing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
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If the capacitance value is increased to generate a longer delay time, then the delay time is improved, but the size of the capacitor and the entire delay circuit increases
Solution Approach 1:
The invention changes the operational parameters of existing circuit components (transistors and capacitor) to achieve the same delay function with different physical dimensions. By adjusting transistor sizes and operating conditions rather than simply increasing capacitance, the circuit achieves the required delay time without proportionally increasing the capacitor size
Solution Approach 2:
The circuit components serve multiple functions: the capacitor is not only for timing but also integrated with transistor switching functions, and the transistor network performs both signal processing and delay generation. This multi-functionality reduces the need for dedicated large-capacitance components solely for timing purposes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit achieves the same delay time as conventional circuits but with a smaller footprint, offering improved compactness and efficiency by optimizing transistor configurations and component interactions.
Implementation Method 1
A delay circuit having a capacitor and generating a delay time according to the capacitance value of this capacitor is known
Implementation Method 2
the first transistor and the fourth transistor are MOS transistors of a first conductivity type which is one of p-type and n-type, and the second transistor and the third transistor are MOS transistors of a second conductivity type which is the other of p-type and n-type
Data Source
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AI summary
Delay circuit (10A to 10G) includes: first to fourth transistors (Q1, Q2, Q5, and Q4); capacitor (21); constant current source (22); and resistor (Q3). The first transistor (Q1) has a gate connected to an input terminal (Ti), a source connected to the first power supply terminal (3), and a drain. The second transistor (Q2) has a gate connected to an input terminal (Ti) and the gate of the first transistor (Q1), a drain connected to the drain of the first transistor (Q1) and the second terminal of the capacitor (21), and a source. The third transistor (Q5) has a gate connected to a node (N1) between the drain of the first transistor (Q1), the drain of the second transistor (Q2), and the second terminal of the capacitor (21), a source connected to the second power supply terminal (4), and a drain. The fourth transistor (Q4) has a gate connected to the node (N1) and the gate of the third transistor (Q5), a drain connected to the drain of the third transistor (Q5) and an output terminal (To), and a source.