MOS Delay Circuit Using Constant Current for Compact Long Delays
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Solution Overview
Problem
Conventional delay circuits require larger capacitance values to generate longer delay times, leading to increased size and complexity, making them less compact.
Innovation Solution
A delay circuit design incorporating MOS transistors of different conductivity types and a capacitor with a constant current source, allowing for the generation of the same delay time with a more compact size by optimizing transistor configurations and resistor connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the capacitance value is increased to generate longer delay times, then the delay time is improved, but the size of the capacitor and the entire delay circuit increases
Solution Approach 1:
The invention changes the operating parameters of the delay circuit by introducing a variable current source that can adjust the charging current to the capacitor. By varying the current parameter, the delay time can be extended without increasing the capacitance value, thus maintaining a compact circuit size while achieving longer delay times.
Solution Approach 2:
The invention employs dynamic control of the charging current through a variable current source that can adjust its output current based on control signals. This dynamic current adjustment allows the delay time to be modulated without changing the physical size of the capacitor or the overall circuit layout, resolving the contradiction between delay time and circuit size.
2Duration of action of moving object
If the capacitance value is increased to achieve the same delay time, then the delay time is maintained, but the number of components and circuit complexity increases
Solution Approach 1:
The variable current source serves multiple functions: it charges the capacitor to generate the delay time, it can be adjusted to extend the delay duration, and it provides a control interface for programmable delay adjustment. This multi-functionality eliminates the need for multiple fixed-value capacitors or complex RC networks, reducing overall circuit complexity while maintaining flexible delay time control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed delay circuit achieves the same delay time as conventional circuits but with a reduced overall size, enabling more compact and efficient designs while maintaining or exceeding delay times of comparable circuits.
Implementation Method 1
A delay circuit having a capacitor and generating a delay time according to the capacitance value of this capacitor is known
Implementation Method 2
a first transistor having a gate connected to the input terminal, a source connected to a first power supply terminal which supplies a first power supply voltage, and a drain
Implementation Method 3
a first constant current source connected between the source of the second transistor and a second power supply terminal which supplies a second power supply voltage different from the first power supply voltage
Data Source
AI summary
Delay circuit includes: first to fourth transistors; capacitor; constant current source; and resistor. The first transistor has a gate connected to an input terminal, a source connected to the first power supply terminal, and a drain. The second transistor has a gate connected to an input terminal and the gate of the first transistor, a drain connected to the drain of the first transistor and the second terminal of the capacitor, and a source. The third transistor has a gate connected to a node between the drain of the first transistor, the drain of the second transistor, and the second terminal of the capacitor, a source connected to the second power supply terminal, and a drain. The fourth transistor has a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and an output terminal, and a source.