MOS Diode Termination Structure for Reverse Voltage Tolerance
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Solution Overview
Problem
MOS diodes face limitations in reverse voltage tolerance and high parasitic capacitance, leading to lower response speed and higher forward voltage drop, especially in high voltage operations.
Innovation Solution
A MOS diode with a termination structure featuring etched shallow trenches, a thicker shielding oxide layer, and a sidewall polysilicon layer within the trenches to reduce parasitic capacitance and enhance reverse voltage tolerance by uniformly spreading the electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a MOS diode uses conventional structure without termination structure, then the device complexity is low, but the reverse voltage tolerance is insufficient
Solution Approach 1:
The patent divides the MOS diode structure into distinct regions: a device region with mesas and a termination region with a trench structure. This segmentation allows the termination region to specifically handle reverse voltage stress while the device region maintains low forward voltage drop, resolving the contradiction between reverse voltage tolerance and device complexity.
Solution Approach 2:
The patent introduces an intermediary termination structure between the device region and the substrate. This termination structure, comprising the trench, oxide layer, and sidewall polysilicon layer, acts as a mediator that distributes electric field stress, thereby enhancing reverse voltage tolerance without requiring complete structural redesign.
2Strength
If a MOS diode uses conventional structure without termination structure, then the manufacturing process is simple, but the reverse voltage tolerance is limited
Solution Approach 1:
The termination structure is formed during the preliminary stages of the manufacturing process, integrating the trench, oxide layer, and polysilicon layer formation into the existing fabrication flow. This preliminary action allows reverse voltage tolerance enhancement without requiring completely new manufacturing steps.
3Reliability
If the MOS diode lacks termination structure, then the parasitic capacitance is high, but adding termination structure increases device complexity
Solution Approach 1:
The patent addresses the parasitic capacitance issue by transitioning from a planar structure to a three-dimensional structure with trenches and sidewall polysilicon layers. This dimensional change effectively reduces parasitic capacitance and improves response speed while managing the associated increase in device complexity.
4Loss of energy
If the MOS diode uses conventional structure, then the forward voltage drop is high, but the reverse voltage tolerance is also limited
Solution Approach 1:
The patent applies local quality by creating different structural characteristics in different regions: the device region maintains features optimized for low forward voltage drop, while the termination region incorporates the trench structure optimized for high reverse voltage tolerance. This localized differentiation resolves the contradiction between forward voltage drop and reverse voltage tolerance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases reverse voltage tolerance and reduces forward voltage drop by minimizing parasitic capacitance and increasing metal contact area, thereby improving the performance of MOS diodes in high voltage applications.
Implementation Method 1
The provision of oxide layer and sidewall polysilicon layer within the trench can advantageously spread the surface electric field to enhance the reverse voltage tolerance of the MOS diode
Implementation Method 2
The shielding oxide layer is thicker than the gate oxide layer to reduce parasitic capacitance
Data Source
AI summary
A MOS diode includes a substrate with a mesa, a P-type semiconductor region with etched shallow trench surrounding the mesa, that cause an increasing metal contact area to reduce Vf value, a gate oxide layer arranged on the mesa, a polysilicon layer arranged on the gate oxide layer, and a shielding oxide layer arranged on the polysilicon layer. The termination structure includes a trench, an oxide layer arranged at least within the trench, at least one sidewall polysilicon layer arranged on the oxide layer within the trench. In the MOS diode, the shielding oxide layer is thicker than the gate oxide layer to prevent leaking current. The oxide layer and the sidewall polysilicon layer can enhance the reverse voltage tolerance of the MOS diode. A metal layer covers the polysilicon region, shielding oxide layer, semiconductor regions with etched shallow trench, termination region and some parts outside the termination region.