MOS Transistor Drain Coupling for High-Speed Signal Transmission
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Solution Overview
Problem
High-frequency operation in semiconductor integrated circuits is hindered by increased capacitance in MOS transistors, particularly in the depletion layer, and RC delay in wiring, which slows down signal transmission and switching operations.
Innovation Solution
A semiconductor integrated circuit design featuring a pair of MOS transistors arranged in the same well with adjacent drain diffusion layers to facilitate rapid charge exchange, combined with a differential wiring structure that applies differential signals to the transistors' gates and a common potential to their sources, enabling fast switching without requiring specific process or material changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MOS transistors are used for high-frequency operation, then the circuit can operate at GHz frequencies, but the capacitance of the depletion layer increases and slows down the state transition
Solution Approach 1:
The patent merges the drain diffusion layers of two MOS transistors into a shared structure within the same well. This allows the depletion layer capacitances to be coupled, enabling charge exchange between them during state transitions. The shared drain structure reduces the total capacitance that must be charged/discharged during switching, thereby decreasing state transition time while maintaining high-frequency operation capability
Solution Approach 2:
The shared drain diffusion layer acts as an intermediary between two MOS transistors. During state transitions, this intermediary structure facilitates rapid charge exchange between the depletion layers of adjacent transistors. The shared drain serves as a charge reservoir that can quickly supply or accept charges, reducing the time required for capacitance charging/discharging and enabling faster switching at GHz frequencies
2Ease of operation
If wiring is used to transmit signals in the entire semiconductor integrated circuit, then signals can be transmitted between components, but RC delay in the wiring slows down signal transmission
Solution Approach 1:
The patent merges power supply and ground lines into a shared wiring structure that serves multiple MOS transistors simultaneously. This consolidated wiring approach reduces the total length and number of individual power/ground traces, thereby reducing cumulative RC delay. The shared wiring structure minimizes the resistive and capacitive effects that would otherwise accumulate across multiple separate connections, enabling faster signal transmission throughout the circuit
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high-speed operation of logic circuits by rapidly exchanging charges between transistors during state transitions, reducing the impact of capacitance and RC delay, thus enabling efficient high-speed signal transmission.
Implementation Method 1
an increase in capacitance of a depletion layer of a drain diffusion layer requires time for charge transfer in the state transition associated with switching operation
Data Source
AI summary
A semiconductor integrated circuit comprising: a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and a wiring structure which is formed to apply differential signals to respective gates of the pair of MOS transistors and to apply a common potential to respective sources of the pair of MOS transistors.