Analog MOS Transistor Drain Extension Implant for CHC Reliability
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Solution Overview
Problem
In dense integrated circuits, angled implants for forming drain extensions in analog MOS transistors often result in reduced channel hot carrier (CHC) reliability due to blockage by the implant mask, leading to suboptimal dopant distribution and junction grading.
Innovation Solution
Implementing exactly four sub-implants with varying twist angles between 5 degrees to 40 degrees and 50 degrees to 85 degrees, all at a consistent tilt angle of at least 15 degrees, to ensure dopant implantation at source/drain gate edges while avoiding blockage by the gate, without using halo implants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If angled implants with zero twist angles are used to form drain extensions, then the implant process is simple and symmetric, but the implant mask blocks the angled implant from reaching the substrate at source/drain edges in dense integrated circuits
Solution Approach 1:
The patent introduces asymmetric twist angles (5-40 degrees from perpendicular) for the implantation process. Instead of using symmetric zero-twist implants that are blocked by the mask, the asymmetric angle allows the ion beam to clear the implant mask and reach the substrate at source/drain edges, achieving both mask clearance and acceptable dopant distribution
Solution Approach 2:
The patent changes the implantation parameters by introducing specific twist angle ranges (5-40 degrees) and tilt angle requirements (at least 15 degrees). These parameter modifications enable the implant beam to navigate around the mask obstruction while maintaining controlled dopant distribution in the substrate
2Manufacturing precision
If twist angles of 45 degrees are used to clear the implant mask, then more dopants reach the substrate, but CHC reliability is less than desired
Solution Approach 1:
The patent optimizes the twist angle parameter to a specific range (5-40 degrees) that balances two competing requirements: clearing the implant mask to achieve adequate dopant distribution while maintaining channel hot carrier reliability. This optimized range provides a compromise between mask clearance and device performance
3Reliability
If multiple sub-implants with varying angles are performed to achieve proper dopant distribution, then CHC reliability improves, but fabrication process complexity increases
Solution Approach 1:
The patent divides the drain extension formation into exactly four discrete sub-implants with specific angle relationships. This segmentation allows precise control over dopant distribution while maintaining a manageable, repeatable process sequence that can be systematically implemented in fabrication
4Manufacturing precision
If tilt angle is increased to clear the implant mask, then dopant implantation succeeds, but the process becomes more complex
Solution Approach 1:
The patent specifies a minimum tilt angle of 15 degrees as an optimal parameter that enables mask clearance while avoiding excessive process complexity. This parameter setting achieves the necessary geometric clearance without requiring overly complex implantation geometries
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances CHC reliability and simplifies the fabrication process by reducing complexity and cost, while improving throughput through the ion implanter, and allows for more precise dopant distribution in the substrate.
Implementation Method 1
implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit
Data Source
AI summary
An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.