MOS ESD Protection Layout With Integrated Dummy-Structure Resistor
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Solution Overview
Problem
Integrated circuits (ICs) are vulnerable to electrostatic discharge (ESD) events, which can cause destruction due to high current levels, and existing ESD protection designs often require large areas and complex circuit layouts to provide adequate protection.
Innovation Solution
A semiconductor layout that includes a MOS transistor, a dummy structure, and a resistor, where the MOS transistor is configured to disperse ESD current and the resistor is electrically coupled to the gate of the MOS transistor to direct ESD current to ground, with the dummy structure comprising at least a poly layer or metal layer, and the resistor overlapping the dummy structure and adjacent to the MOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ESD protection circuits are designed with separate resistor and dummy structure components, then adequate ESD protection is provided, but the occupied area and circuit layout complexity increase significantly
Solution Approach 1:
The patent combines the resistor and dummy structure into a single integrated component where the dummy structure serves dual purposes: maintaining circuit layout regularity and providing ESD protection functionality. The resistor is formed within the same structural footprint as the dummy structure, eliminating the need for separate dedicated resistor areas and reducing total occupied space while maintaining adequate ESD protection capability.
2Reliability
If traditional ESD protection circuits are designed with separate resistor and dummy structure components, then adequate ESD protection is provided, but the circuit layout complexity increases
Solution Approach 1:
The dummy structure is designed to serve multiple functions simultaneously: it maintains the regularity of the circuit layout by occupying necessary structural space, provides ESD protection through its inherent properties, and houses the resistor functionality within its boundaries. This multi-functionality eliminates the need for separate dedicated components and simplifies the overall circuit layout while ensuring adequate ESD protection.
3Reliability
If the resistor is positioned far from the core circuit for safety margins, then ESD current dispersion is improved, but the occupied area and layout complexity increase
Solution Approach 1:
The patent utilizes vertical layering and overlapping in the layout design, allowing the resistor to be positioned in a different spatial dimension (overlapping with the dummy structure) rather than requiring horizontal separation. This dimensional approach enables the resistor to be closely positioned to the core circuit for effective ESD current dispersion while containing the overall footprint within the dummy structure's boundaries, thus reducing occupied area without compromising protection effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively protects the core circuit from ESD events by dispersing current and reducing the area and complexity of the protection circuit, enhancing ESD protection without occupying large areas or rearranging the circuit layout.
Implementation Method 1
The MOS transistor is configured to protect the core circuit by dispersing an ESD current thereacross during an ESD event
Implementation Method 2
The resistor is electrically coupling to a gate of the MOS transistor for creating a bias on the gate to directing an ESD current to a ground
Data Source
AI summary
An electrostatic discharge (ESD) protection circuit is provided. The protection circuit includes a MOS transistor and a resistor. The MOS transistor is electrically coupled to a core circuit. The resistor is electrically coupling to a gate of the MOS transistor for creating a bias on the gate to directing an ESD current to a ground when an ESD event occurs on the core circuit. A layout of the MOS transistor is spaced apart from a layout of the core circuit by a layout of a dummy structure. The resistor is formed by utilizing a portion of the dummy structure.