MOS ESD Protection Circuit for Floating Node and Latch-Up Control
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Solution Overview
Problem
The technical challenge is to provide an effective electro-static discharge protection circuit for semiconductor chips, particularly in CMOS circuits, that prevents instability and ensures proper operation by eliminating floating nodes during electro-static discharge events, while effectively managing parasitic bipolar circuits to avoid latch-up and ensure stable discharge protection.
Innovation Solution
The solution involves a circuit structure with input and ground pad terminals, MOS transistors, and parasitic bipolar transistors that are connected in specific configurations to manage static electricity, ensuring no floating nodes and preventing latch-up, using MOS transistors and parasitic bipolar transistors to discharge both positive and negative static electricity safely.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD elements are used in BCD process, then electro-static discharge protection is provided, but latch-up occurs and circuit stability deteriorates
Solution Approach 1:
The patent introduces a dedicated control circuit as an intermediary between the ESD element and the internal circuit. This control circuit monitors the state of the ESD element and actively controls the switch connection to prevent latch-up, thereby maintaining circuit stability while preserving ESD protection functionality.
Solution Approach 2:
The control circuit automatically detects when the ESD element enters a latch-up state and autonomously activates the switch to disconnect the ESD element from the internal circuit. This self-service mechanism prevents the need for external intervention and maintains circuit stability without adding complex control logic.
2Object-affected harmful factors
If ESD element is connected to input/output pad, then electro-static discharge protection is achieved, but floating nodes cause circuit instability
Solution Approach 1:
The control circuit implements a feedback mechanism that continuously monitors the voltage state of nodes connected to the ESD element. When a floating node is detected (indicated by abnormal voltage levels), the control circuit activates the switch to disconnect the ESD element, thereby stabilizing the circuit nodes while maintaining protection capability.
3Area of stationary object
If BCD process is used to form various transistors on single substrate, then area is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The control circuit is designed with multi-functionality to handle different ESD protection scenarios (latch-up prevention, floating node detection, and normal operation) using a unified structure. This universal design approach minimizes the additional complexity introduced by the control circuit while maximizing its protective capabilities across various operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively protects internal semiconductor chip circuits from static electricity by ensuring stable operation and preventing latch-up, allowing for accurate and flexible electro-static discharge protection without node floating, effectively managing both positive and negative static electricity discharges.
Implementation Method 1
electro-static discharge protection circuit
Implementation Method 2
a first parasitic bipolar transistor formed by the source, drain, and body of the first MOS transistor; a second parasitic bipolar transistor formed by the source, drain, and body of the second MOS transistor
Data Source
AI summary
The present invention provides an electro-static discharge protection circuit including an input pad terminal; a ground pad terminal; a first Metal Oxide Semiconductor (MOS) transistor, wherein a source or drain terminal of the first MOS transistor is electrically connected to the input pad terminal and a gate of the first MOS transistor is electrically connected to the ground pad terminal; a second MOS transistor, wherein a source or drain terminal of the second MOS transistor is electrically connected to the ground pad terminal and a gate of the second MOS transistor is electrically connected to the input pad terminal; a common node in which the remaining terminal not connected to the input terminal among the source or drain of the first MOS transistor and the remaining terminal not connected to the ground terminal among the source or drain of the second MOS transistor are electrically connected to each other.