Compact MOS ESD Protection Circuit With Shared Substrate Resistor

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Solution Overview

Problem

Existing ESD protection devices for integrated circuits can be triggered during normal operation due to uncontrolled environmental conditions, leading to potential damage and errors, and they often occupy significant surface area, especially when distributed across multiple signal terminals.

Innovation Solution

The integration of MOS transistors with a common resistor coupling the substrate and gate to the reference terminal, allowing for direct or indirect gate-reference coupling, prevents premature triggering and reduces the footprint by enabling a compact, hybrid operation-compatible ESD protection system across multiple terminals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ESD protection devices are distributed across multiple signal terminals, then protection coverage is improved, but surface area occupied increases

Engineering Contradiction:
Improveprotection coverageVSAvoidsurface area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines multiple ESD protection devices into a single integrated structure where multiple MOS transistors share common components including a common substrate resistor, common source region, and common drain region. This merging approach maintains comprehensive protection across multiple signal terminals while significantly reducing the total surface area required compared to distributed separate devices.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If hybrid operation transistors are used for ESD protection, then resistance to ionizing radiation is improved, but device complexity increases

Engineering Contradiction:
Improveradiation resistanceVSAvoidtransistor structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The hybrid operation transistor serves multiple functions within a single device structure: it provides ESD protection, exhibits resistance to ionizing radiation, and maintains low power consumption during normal operation. The same transistor structure that enables radiation resistance through its bipolar component also provides the ESD protection capability, eliminating the need for separate dedicated ESD devices and reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively absorbs electrostatic discharge currents between any pair of terminals, preventing damage and errors while maintaining a reduced footprint, even during operation, by ensuring the gate of the MOS transistors is not prematurely polarized and allowing for efficient triggering of the protection devices.

Implementation Method 1

An electrostatic discharge generally results in a current peak varying in size (amplitude, magnitude) and brevity (time) between two terminals of an electronic module of the integrated circuit

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Implementation Method 2

the breakdown of the drain-substrate or source-substrate junction of the first MOS transistor TR1

Methodology Applied
Scientific EffectBreakdown: Avalanche Breakdown

Implementation Method 3

Hybrid operation transistors are MOS transistors comprising a parasitic bipolar transistor the operation of which involves an operation of this bipolar transistor and an operation of the MOS transistor in a sub-threshold mode

Methodology Applied
Scientific EffectParasitic bipolar transistor operation:

Data Source

PatentUS11887982B2Compact protection device for protecting an integrated circuit against electrostatic discharge
Publication Date: 2024.01.30 STMICROELECTRONICS FRANCE
  • US11887982B2 patent drawing
  • US11887982B2 patent drawing
  • US11887982B2 patent drawing

AI summary

An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.