MOS Fin Device With Thick Gate Oxide For High Voltage Operation
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Solution Overview
Problem
Current semiconductor technologies, such as FinFETs, are limited to operating voltages of up to 1.8 V-2.5 V, which is insufficient for certain applications like SoC, RF, and high-voltage memory, and adding complexity and cost with dual gate oxide processes or complex circuit techniques.
Innovation Solution
The technique involves forming MOS fin devices with thicker gate oxide by controlling dielectric thickness through gate mask alignment, allowing for higher operating voltages without additional process costs, and enabling multiple gate dielectric thicknesses, while reducing gate parasitic resistance and maintaining RF capacitor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If dual gate oxide processes are used to achieve higher operating voltages, then the operating voltage range is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies local quality by creating different gate oxide thicknesses in different regions of the semiconductor device. Specifically, first gate oxide is formed with a first thickness in a first region, while second gate oxide is formed with a second thickness in a second region. This allows different portions of the device to have optimized characteristics for their specific functions, enabling higher operating voltages where needed without increasing overall process complexity.
Solution Approach 2:
The patent segments the gate oxide structure into multiple distinct layers and regions. By dividing the gate oxide into first gate oxide and second gate oxide with different thicknesses and materials, the device can achieve multiple operating voltage ranges simultaneously. This segmentation approach avoids the need for completely separate dual-gate-oxide processes while still achieving the desired voltage range expansion.
2Ease of manufacture
If conventional FinFET structures are used, then manufacturing is simplified, but the operating voltage is limited to 1.8 V-2.5 V
Solution Approach 1:
The patent changes key parameters of the gate oxide structure to achieve higher operating voltages while maintaining manufacturing simplicity. By adjusting the thickness, material composition, and spatial distribution of gate oxide layers, the device can operate at voltages exceeding the conventional 1.8 V-2.5 V range. This is achieved through controlled formation of first and second gate oxide with different characteristics during the fabrication process.
Solution Approach 2:
The patent employs composite materials by combining different oxide materials in the gate structure. The first gate oxide and second gate oxide are formed with different material compositions and thicknesses, creating a composite gate dielectric structure. This composite approach enables the device to achieve higher operating voltages while still using standard semiconductor manufacturing processes.
3Power
If thicker gate oxide is formed to enable higher operating voltages, then the operating voltage is improved, but the gate parasitic resistance increases
Solution Approach 1:
The patent applies local quality by positioning different gate oxide thicknesses in different spatial regions. The first gate oxide with first thickness is formed in a first region, while the second gate oxide with second thickness is formed in a second region. This spatial differentiation allows the device to achieve higher operating voltages in regions where thicker oxide is beneficial, while maintaining thinner oxide in regions where lower parasitic resistance is critical for performance.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a semiconductor device and techniques for fabricating a semiconductor device. In certain aspects, the semiconductor device includes a fin, a first non-insulative region disposed adjacent to a first side of the fin, and a second non-insulative region disposed adjacent to a second side of the fin. In certain aspects, the first non-insulative region and the second non-insulative region are separated by a trench, at least a portion of the trench being filled with a dielectric material disposed around the fin.