MOS Full-Wave Detection Circuit for High-Frequency Low-Power Signals
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Solution Overview
Problem
Existing UWB-IR communication systems face challenges with high-frequency signal detection due to insufficient operation speed and power consumption, and the inability to effectively handle large signal variations and low signal levels, particularly with existing envelope detection circuits that rely on PN junction diodes and bi-polar transistors.
Innovation Solution
An electronic circuit utilizing two drain ground amplifying transistors and negative feedback paths to selectively amplify absolute values of input signals, enabling full wave rectification without PN junction diodes, allowing for high-speed and low-power operation suitable for UWB-IR communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If envelope detection circuit uses PN junction diode and bi-polar transistor, then detection capability is achieved, but operation speed is insufficient and power consumption increases
Solution Approach 1:
The patent replaces PN junction diodes and bi-polar transistors with MOS transistors operating in saturation region. This substitution eliminates the need for slow bi-polar transistor switching and high-power diode rectification, achieving high-speed operation compatible with CMOS processes while reducing power consumption through MOS transistor's voltage-controlled operation mode.
Solution Approach 2:
The patent changes the operating parameters by using MOS transistors in saturation region rather than linear region, and operates at high frequency close to element performance limits. This parameter change enables the circuit to achieve both high-speed operation and low power consumption simultaneously, resolving the traditional trade-off between speed and power.
2Speed
If frequency conversion is performed for high frequency signals, then detection becomes possible, but phase synchronization accuracy requirements increase and errors occur when not synchronized
Solution Approach 1:
The patent extracts and eliminates the frequency conversion stage from the detection system. By directly detecting high-frequency signals using MOS transistors in saturation region, the system removes the intermediate frequency conversion step that requires phase synchronization, thereby eliminating synchronization errors and improving detection reliability.
Solution Approach 2:
The patent introduces MOS transistors operating in saturation region as an intermediary element that can directly handle high-frequency signals without frequency conversion. This intermediary enables direct high-frequency detection while maintaining reliability, avoiding the need for phase-synchronized frequency conversion stages.
3Ease of manufacture
If square detection circuit is used, then circuit integration is possible, but signal level variations are promoted and performance lowers when receiving signal level is low
Solution Approach 1:
The patent changes the detection method from squaring operation to absolute value detection using MOS transistors in saturation region. This parameter change maintains circuit integrability in CMOS processes while avoiding the promotion of signal level variations, thereby improving detection accuracy especially for low-level receiving signals.
4Reliability
If full wave rectification is performed for UWB-IR communication, then signal detection is achieved, but operation speed is only a fraction of element performance limit
Solution Approach 1:
The patent replaces traditional full wave rectification circuits with a direct absolute value detection circuit using MOS transistors in saturation region. This substitution eliminates the multi-stage rectification process that limits speed to a fraction of element performance, achieving operation speeds close to the MOS transistor performance limit while maintaining reliable signal detection.
Data Source
AI summary
An electronic circuit includes: a first amplifying circuit to which a first input signal is inputted; a second amplifying circuit to which a second input signal is inputted; a first drain ground amplifying transistor provided between a first power source node and an output node with control over the gate by the output from the first amplifying circuit; a second drain ground amplifying transistor provided between the first power source node and the output node with control over the gate by the output from the second amplifying circuit; a common load element provided between the output node and a second power source node; a first negative feedback path for negative feedback from the output node to the input of the first amplifying circuit; and a second negative feedback path for negative feedback from the output node to the input of the second amplifying circuit.