MOS Gate Contacts Over Channel
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Solution Overview
Problem
Conventional MOS transistor designs face challenges in reducing gate resistance due to over-etching issues and material properties, which limit the placement of gate contacts over the channel, affecting RF performance and noise figures.
Innovation Solution
The placement of gate contacts over the channel is enabled through the use of etch-stop layers and higher conductivity metals, along with controlled fabrication techniques to prevent over-etching and charging, allowing for reduced gate resistance and increased conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contacts are placed over the channel, then gate resistance is reduced, but over-etching may consume the gate and lead to charging damage
Solution Approach 1:
An etch-stop layer is introduced between the gate contact and the gate electrode to prevent over-etching damage. This intermediary layer stops the etch process before it can reach and damage the gate, allowing safe contact placement over the channel while maintaining low gate resistance
Solution Approach 2:
The etch-stop layer is placed in advance to counteract the harmful effect of over-etching. By positioning this protective layer before the gate electrode, the design preemptively prevents charging damage and gate consumption that would otherwise occur during contact formation
2Object-affected harmful factors
If gate contacts are placed away from the channel, then over-etching damage is avoided, but gate resistance increases affecting RF performance
Solution Approach 1:
The contact placement moves from the lateral dimension (away from channel) to the vertical dimension (over the channel but stopped by etch-stop layer). This dimensional shift allows contacts to be positioned over the channel for low resistance while the etch-stop layer prevents vertical over-etching damage
3Reliability
If the gate electrode width is increased, then gate resistance is reduced, but device area increases
Solution Approach 1:
The gate resistance reduction is achieved through segmented contact placement (multiple contacts over the channel) rather than increasing the continuous gate width. This segmentation approach lowers resistance by providing multiple parallel current paths without expanding the overall device footprint
Data Source
AI summary
A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.