MOS Gate Driver Timing With Auxiliary Transistors Against Through Current

Solution Overview

Problem

Conventional driver circuits face issues with parasitic capacitance affecting switching behavior and causing through current due to increased gate impedance, which existing technologies have not effectively addressed.

Innovation Solution

The driver circuit design includes auxiliary pMOS and nMOS transistors with controlling circuits that generate signals with specific delay times to synchronize the operation of these transistors with the output MOS transistors, effectively reducing the impact of parasitic capacitors and suppressing through current by keeping the output pMOS and nMOS transistors in the appropriate states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If gate impedance is increased to adjust the through rate, then the through rate is improved, but parasitic capacitance affects switching and causes through current

Engineering Contradiction:

Improvethrough rateVSAvoidswitching behavior

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The auxiliary transistor is activated in advance before the output transistor switches on. This preliminary action ensures that the gate impedance is already adjusted to the appropriate level before the main switching event occurs, preventing the parasitic capacitance from causing improper switching behavior or through current.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The auxiliary transistor serves as an intermediary element that indirectly controls the gate impedance of the output transistor. By using this intermediate component to adjust the impedance, the patent avoids directly modifying the output transistor's switching characteristics, thereby preventing parasitic capacitance issues while maintaining through rate control.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If gate impedance is increased to adjust the through rate, then the through rate is improved, but through current occurs between output transistors

Engineering Contradiction:

Improvethrough rateVSAvoidthrough current

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The auxiliary transistor is activated in advance before the output transistor switches on. This preliminary action ensures that the gate impedance is already adjusted to the appropriate level before the main switching event occurs, preventing the parasitic capacitance from causing improper switching behavior or through current.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The auxiliary transistor serves as an intermediary element that indirectly controls the gate impedance of the output transistor. By using this intermediate component to adjust the impedance, the patent avoids directly modifying the output transistor's switching characteristics, thereby preventing parasitic capacitance issues while maintaining through rate control.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8692577B2Driver circuit

Publication Date: 2014.04.08 KK TOSHIBA

AI summary

The driver circuit includes a first controlling circuit that outputs, to a gate of the auxiliary pMOS transistor, a first controlling signal that rises in synchronization with a rising of the first pulse signal and falls after a delay from a falling of the first pulse signal. The driver circuit includes a second controlling circuit that outputs, to a gate of the auxiliary nMOS transistor, a second controlling signal that rises in synchronization with a rising of the second pulse signal and falls after a delay from a falling of the second pulse signal.