MOS Gate Electrode Nitrogen Gradient Work Function Stability
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Solution Overview
Problem
Conventional metal oxide semiconductor (MOS) transistors face challenges in maintaining a stable work function of the gate electrode during thermal treatment, leading to uncontrollable threshold voltage and deteriorated electrical characteristics due to reactions between the lower and upper metal films in the gate conductive layer pattern.
Innovation Solution
A gate electrode structure is implemented with a first gate conductive layer pattern having a nitrogen concentration gradient and a second gate conductive layer pattern with lower resistance, preventing reactions and maintaining the desired work function even after thermal treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate conductive layer pattern including doped polysilicon is used, then the Fermi-level pinning effect occurs causing deterioration of impurity mobility, but the work function can be adjusted through doping
Solution Approach 1:
The patent changes the material parameter from doped polysilicon to metal (such as tungsten, titanium, or their nitrides), fundamentally altering the electrical characteristics and eliminating the Fermi-level pinning effect. This material substitution resolves the contradiction by providing both high impurity mobility and controllable work function through metal selection and thickness control.
Solution Approach 2:
The patent employs a composite gate structure consisting of multiple metal layers (lower metal film for work function adjustment and upper metal film for wiring). This composite approach allows independent optimization of each layer's properties, achieving both high mobility and precise work function control through the combination of different metal materials.
2Reliability
If metal is used for the gate conductive layer pattern to reduce Fermi-level pinning effect, then impurity mobility improves, but the work function changes during thermal treatment process
Solution Approach 1:
The patent performs preliminary work function adjustment by selecting specific metal materials and controlling their thickness before the thermal treatment process. The lower metal film is designed with appropriate thickness (e.g., 5-20 nm) and material composition to establish the desired work function in advance, which then remains stable during subsequent thermal processing.
Solution Approach 2:
The patent introduces a lower metal film as an intermediary layer between the gate insulation layer and the upper metal film. This intermediate layer acts as a buffer that prevents direct reaction between the upper metal and gate insulation, while also providing work function control, thus stabilizing the overall gate structure during thermal treatment.
3Ease of manufacture
If the lower metal film thickness is increased to adjust work function, then work function control improves, but the gate structure complexity increases
Solution Approach 1:
The patent controls the thickness parameter of the lower metal film within a specific range (5-20 nm) to achieve work function adjustment without excessive thickness increase. By optimizing this parameter, the patent balances work function control capability with structural simplicity, avoiding unnecessary complexity while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures proper electrical characteristics, such as desired threshold voltage and flat band voltage, by preventing work function changes in the gate electrode during thermal treatment, thereby improving the transistor's performance and manufacturing reliability.
Implementation Method 1
The first gate conductive layer pattern has a nitrogen concentration gradient
Implementation Method 2
a thermal treatment process for activating the impurities doped into the semiconductor substrate. The thermal treatment process is usually performed at a temperature above about 1,000° C.
Implementation Method 3
the gate insulation layer pattern is usually formed using a material having a high dielectric constant
Data Source
AI summary
A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes a first gate conductive layer pattern and a second gate conductive layer pattern. The first gate conductive layer pattern has a nitrogen concentration gradient gradually increasing from a lower portion of the first gate conductive layer pattern to an upper portion of the first gate conductive layer pattern. The second gate conductive layer pattern includes a material having a resistance substantially lower than a resistance of the first gate conductive layer pattern.