Planar MOS Gate Grid Layout for Higher Breakdown Voltage
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Solution Overview
Problem
Conventional planar MOS devices have a lowered breakdown voltage due to depletion layers at gate intersections failing to merge, leading to instability and a narrowed operating range.
Innovation Solution
A semiconductor device with ion-implanted regions and a patterned field oxide layer that forms a grid, where the ion-implanted regions are positioned to facilitate merging of depletion layers at gate intersections, enhancing breakdown voltage and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar MOS device structure is used without implantation mask for JFET implantation, then manufacturing process is simple, but depletion layers at gate intersections fail to merge, resulting in lowered breakdown voltage and device instability
Solution Approach 1:
The patent applies preliminary action by forming a patterned field oxide layer before JFET implantation to predefine the implantation regions. This mask layer is prepared in advance to ensure proper dopant placement underneath gate intersections, enabling depletion layer merging while maintaining manufacturing feasibility through a structured process approach
Solution Approach 2:
The patterned field oxide layer serves as an intermediary element between the implantation process and the final device structure. It acts as a temporary mask that guides dopant placement during JFET implantation and is subsequently removed, enabling precise control over implantation regions without requiring complex direct patterning
2Reliability
If dopant concentration in JFET regions is increased to improve breakdown voltage, then depletion layers can merge better, but device operating range is narrowed due to excessive doping
Solution Approach 1:
The patent applies local quality by creating spatially varying dopant concentrations through the patterned field oxide mask. Different regions receive different amounts of dopant: gate intersection areas receive higher concentration to promote depletion layer merging and increase breakdown voltage, while non-intersection gate regions receive lower concentration to maintain device operating range and performance
Solution Approach 2:
The implantation process is segmented into distinct regions using the patterned field oxide layer as a mask. The dopant implantation is divided into first JFET implantation regions underneath gate intersections and second JFET implantation regions underneath non-intersecting gate regions, allowing independent optimization of dopant concentration for each segment to simultaneously achieve high breakdown voltage and broad operating range
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases breakdown voltage and improves device stability by ensuring depletion layers at gate intersections merge effectively, thereby expanding the operating range.
Implementation Method 1
performing JFET implantation for the gate regions and the plurality of gate intersections, using the patterned field oxide layer as another ion implantation mask
Implementation Method 2
followed by a diffusion process, to form first JFET implantation regions configured to be underneath the plurality of gate intersections
Data Source
AI summary
The present disclosure provides a metal oxide semiconductor device and a method for manufacturing the same. The metal oxide semiconductor device includes a semiconductor substrate, a patterned field oxide layer, first JFET implantation regions and second JFET implantation regions. Active regions and gate regions are formed on an upper surface of the semiconductor substrate, each active region is surrounded by two or more of the gate regions, and the gate regions form a grid and some gate regions overlap to form gate intersections. The first JFET implantation regions are formed by implanting ions underneath the gate intersections of the upper surface of the semiconductor substrate. Orthogonal projections of the first JFET implantation regions and the field oxide layer onto the substrate don't overlap. The second JFET implantation regions are formed by implanting ions into the upper surface of the semiconductor substrate and located underneath the gate regions that are not gate intersections.