MOS Gate Conductive Plate Layout for Leakage and Power Control

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Solution Overview

Problem

MOS transistors experience increased power consumption due to substrate current during the on state, resulting from a redistribution of the electrical field caused by reducing the gate electrode length, which moves the highest electrical field deeper into the substrate, leading to gate-induced drain leakage.

Innovation Solution

The arrangement of conductive plates in direct contact with the gate electrode, extending to overlap areas between the gate electrode and the source and drain regions, redistributes the electrical field back towards the substrate surface, reducing substrate current during the on state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the gate electrode length is reduced, then the transistor switching speed is improved, but the electrical field redistributes deeper into the substrate causing increased substrate current and power consumption

Engineering Contradiction:
Improvetransistor switching speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

A conductive plate is introduced as an intermediary element between the gate electrode and the substrate. This conductive plate redistributes the electrical field in a controlled manner, preventing the field from penetrating too deeply into the substrate while maintaining the short gate length benefits. The conductive plate acts as a mediator that decouples the relationship between gate length reduction and substrate field penetration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The conductive plate is positioned specifically in the region where the electrical field redistribution occurs (between the gate electrode and substrate). By applying conductivity locally in this critical region rather than throughout the entire structure, the patent addresses the specific problem of substrate field penetration while maintaining other design requirements.

Inventive Principle:
Principle #3Local quality

2Length of moving object

If the gate electrode length is reduced, then the device miniaturization is achieved, but gate-induced drain leakage increases due to electrical field redistribution

Engineering Contradiction:
Improvegate electrode lengthVSAvoidgate-induced drain leakage
Core Design Contradiction:
Length of moving objectVSObject-generated harmful factors

Solution Approach 1:

The conductive plate serves as an intermediary that modifies the electrical field distribution pattern. By introducing this intermediate conductive element, the patent prevents the direct coupling between the short gate electrode and the substrate that causes gate-induced drain leakage, while still allowing the gate length to remain short for miniaturization.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Power

If the electrical field is allowed to redistribute naturally with reduced gate length, then the transistor on-state current is improved, but substrate current increases leading to higher power consumption

Engineering Contradiction:
Improvetransistor on-state currentVSAvoidsubstrate current
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

The conductive plate is strategically placed in the specific region where electrical field redistribution occurs (between gate and substrate). This localized intervention allows the electrical field to redistribute beneficially for on-state current while preventing excessive field penetration into the substrate that would cause substrate current and energy loss.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250275166A1Semiconductor device and method of fabricating a semiconductor device
Publication Date: 2025.08.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250275166A1 patent drawing
  • US20250275166A1 patent drawing
  • US20250275166A1 patent drawing

AI summary

A semiconductor device and a method of fabricating the same are provided. The method includes steps of forming a source region and a drain region in a substrate; forming a gate structure on the substrate, wherein the source region and the drain region are disposed on opposite sides of the gate structure and separated from the gate structure by a distance; depositing an inter-layer dielectric (ILD) layer over the substrate and the gate structure; forming a first trench in the ILD layer, wherein the first trench exposes a first portion of the gate structure and overlies an area between the gate structure and one of the source and drain regions from a top-view perspective; and depositing a first conductive material in the first trench to form a conductive plate, wherein the conductive plate is electrically connected to the gate structure.