MOS Gate and RC Element Integration for Area-Efficient Layout
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently manufacturing MOS transistors, capacitors, and resistance elements with area-efficient designs, as existing technologies struggle to optimize the placement and functionality of these components within a limited semiconductor substrate area.
Innovation Solution
The semiconductor device incorporates a resistance-capacitance element with a polysilicon conductive layer and a metal conductive layer, allowing for both capacitor and resistance element functionality, and a method involving multiple insulating and conductive films, trench formation, and metal deposition to create efficient gate electrodes and resistor wiring, enabling area-efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate manufacturing processes are used for MOS transistors, capacitors, and resistance elements, then each component can be optimized for its specific function, but the manufacturing process complexity and area consumption increase
Solution Approach 1:
The patent applies multi-functionality by designing a unified manufacturing process that can produce MOS transistors, capacitors, and resistance elements using the same sequence of steps. The key is that the gate electrode pattern serves multiple purposes: it defines transistor gates, capacitor electrodes, and resistance element regions. By making the process universal, the patent reduces manufacturing complexity while maintaining the ability to optimize each component type through selective material deposition and patterning in specific regions.
2Reliability
If separate manufacturing processes are used for MOS transistors, capacitors, and resistance elements, then each component can be optimized for its specific function, but the semiconductor substrate area consumption increases
Solution Approach 1:
The patent merges the manufacturing of capacitors and resistance elements with the transistor fabrication process. Specifically, the gate electrode deposition and patterning steps that define transistor gates are simultaneously used to create capacitor electrodes and resistance element structures. This combining of operations allows multiple components to share the same physical space and process steps, significantly reducing the total substrate area required compared to separate dedicated processes for each component type.
3Reliability
If high-resistance material is used for resistance elements, then the resistance element performance is optimized, but the available metal materials for gate electrodes are limited
Solution Approach 1:
The patent applies local quality by using different metal materials in different regions of the semiconductor device. Specifically, high-resistance metal materials are deposited and patterned only in regions where resistance elements are required, while low-resistance metal materials are used for gate electrodes and interconnects. This spatial differentiation allows the device to achieve both high-resistance performance where needed and low-resistance performance where required, without compromising material selection flexibility.
Data Source
AI summary
According to one embodiment, transistors and a resistance-capacitance element are provided. The transistors each have a gate insulating film with a gate dielectric film and a gate electrode of a metal material. The resistance-capacitance element is provided by stacking a first insulating film, a first conductive layer, a stopper insulating film, a second insulating film, and a second conductive layer on an upper surface of a semiconductor substrate. The second insulating film includes the gate dielectric film like the gate insulating film. The second conductive layer is made of the same metal material as the gate electrode. The first conductive layer is a conductive material having a higher resistance than the second conductive layer.