MOS Gate Modeling via Slice Segmentation for Stress and Mobility Analysis
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Solution Overview
Problem
Current circuit design technologies fail to accurately account for varying mechanical stresses across transistor geometries, leading to changes in electron mobility and increased leakage current, which can result in unmanageable standby power dissipation and reliability issues in nanometer-scale circuits.
Innovation Solution
A computer-implemented method and simulator that breaks down a non-rectangular MOS gate into slices, determining slice-specific parameters such as gate width, length, and stress profiles to calculate length-based and carrier mobility-based currents, allowing for the determination of effective gate length and mobility, thereby modeling the gate's electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If constant electron mobility is assumed through each MOS gate profile, then design complexity is reduced, but accuracy of threshold voltage and carrier mobility determination deteriorates
Solution Approach 1:
The MOS gate is divided into multiple slices along its length, with each slice having its own stress profile and carrier mobility calculation. This segmentation allows the system to account for varying mechanical stresses at different positions without requiring a completely complex continuous analysis, thus balancing accuracy with computational feasibility
Solution Approach 2:
Each slice of the MOS gate is assigned local stress profile characteristics and corresponding carrier mobility values based on its specific position and stress conditions. This local quality approach enables accurate representation of threshold voltage and carrier mobility variations at different gate locations while maintaining overall design manageability
2Area of moving object
If geometries of layers such as silicon dioxide are reduced, then circuit density is improved, but leakage current increases
Solution Approach 1:
The gate structure is segmented into multiple slices, allowing leakage current to be calculated and analyzed at each individual slice level. This enables identification of specific regions contributing most to leakage current, facilitating targeted optimization of dielectric layers and stress profiles to reduce overall leakage while maintaining high circuit density
Solution Approach 2:
The system calculates and optimizes multiple parameters including slice gate length, slice gate width, stress profile, and carrier mobility for each slice. By adjusting these parameters, the system can reduce leakage current through optimized dielectric geometry and stress management while maintaining high circuit density
3Measurement precision
If stress inducing materials are used to improve electron mobility, then carrier mobility is improved, but threshold voltage changes beyond design tolerances
Solution Approach 1:
The gate is divided into slices, each with independently calculated stress profiles and carrier mobility values. This allows the system to identify regions where stress inducing materials provide beneficial mobility enhancement while detecting regions where the same materials cause excessive threshold voltage shifts, enabling localized optimization
Solution Approach 2:
Each slice is assigned its own stress profile characteristics based on local material composition and geometry. This local quality approach enables the system to optimize carrier mobility in specific regions using stress inducing materials while controlling threshold voltage changes in other regions, achieving both improved mobility and maintained manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate determination of MOS gate functional limitations, effectively managing leakage and drive currents by accounting for stress variations, reducing standby power dissipation and improving reliability in nanometer-scale circuits.
Implementation Method 1
the generally rectangular cross-section of a gate and channel can have a stress profile that varies as a function of displacement from a gate input or other threshold, but not necessarily only because of the displacement from gate input
Implementation Method 2
These changes, if not accounted for can cause the threshold voltage, Vth, carrier mobility or both to change beyond design tolerances
Implementation Method 3
Leakage current is current that flows across a dielectric area between two nearby conductors while a gate is off. Drive current is the current that flows to a drain of a gate or transistor when the gate is turned on
Data Source
AI summary
Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.