Silicided MOS Gate Structure for Dielectric Stress Relief
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Solution Overview
Problem
Highly integrated semiconductor devices face issues with gate dielectric layers experiencing excessive stress, leading to phase changes and deteriorated characteristics during fabrication.
Innovation Solution
A method for forming a MOS transistor with a silicide layer involving ion bombardment processes to create vacancies in gate electrode material layers, followed by silicidation, which alleviates stress and maintains performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If highly integrated semiconductor devices are fabricated with conventional gate structures, then device integration density is improved, but gate dielectric layers experience excessive stress causing phase changes and characteristic deterioration
Solution Approach 1:
The gate electrode is divided into multiple segments (lower gate electrode layer, intermediate gate electrode layer, upper gate electrode layer) with different materials and functions. This segmentation allows each layer to contribute differently to stress management, enabling high integration density while maintaining gate dielectric stability through the combined effect of multiple specialized layers.
Solution Approach 2:
The gate electrode uses a composite structure combining different materials (e.g., cobalt, nickel, tungsten, or molybdenum for lower layer; platinum, iridium, or ruthenium for upper layer). This composite material approach enables optimization of each material's properties to collectively manage stress on the gate dielectric while maintaining electrical performance for high integration.
2Reliability
If ion bombardment processes are performed on gate electrode material layers, then vacancies are created to reduce stress on gate dielectric layers, but additional process steps are added
Solution Approach 1:
Ion bombardment is performed as a preliminary action during gate electrode formation to pre-create vacancies that will later accommodate stress relief. By performing this action early in the fabrication process, the subsequent silicidation step can efficiently utilize these pre-formed vacancies to reduce stress without requiring additional complex process steps.
Solution Approach 2:
The ion bombardment process acts as an intermediary mechanism that creates vacancies serving as stress relief pathways. These vacancies function as intermediaries between the gate electrode material and the gate dielectric layer, allowing stress to be redistributed and reduced without direct mechanical intervention.
3Reliability
If silicide layers are formed in gate electrode layers to create lower and upper gate electrode layers, then stress distribution is improved, but manufacturing complexity increases
Solution Approach 1:
Silicide layers are formed locally within specific regions of the gate electrode layers rather than uniformly throughout. This local quality approach allows stress relief to be concentrated where most needed (at the interfaces with gate dielectric) while keeping other regions simpler, thereby improving stress distribution without proportionally increasing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces stress on gate dielectric layers, preventing phase changes and maintaining the performance of the MOS transistor.
Implementation Method 1
performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions
Implementation Method 2
forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer
Data Source
AI summary
A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.