MOS Transistor Gate Trench Abutting Drain Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need to increase on-state current densities in drain extended MOS (DEMOS) and laterally diffused MOS (LDMOS) transistors without compromising breakdown voltage, hot carrier injection, and safe operating area, particularly by reducing electrical resistance in confined semiconductor regions between isolation dielectric layers and source regions.
Innovation Solution
The solution involves forming an integrated circuit with a gate trench abutting an isolation dielectric layer over a drift region, where a body well overlaps the gate trench bottom surface, and a source diffused region overlaps the gate trench surface within the body well, allowing current to flow directly from the inversion layer to the drift region without passing through confined semiconductor regions, thereby reducing series resistance and enhancing on-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistor structures are used, then manufacturing is simpler, but on-state current density is insufficient
Solution Approach 1:
The patent transitions from planar gate structures to vertically extended gate trenches that penetrate through the drift region to the substrate. This dimensional change creates additional current flow paths and reduces resistance in the on-state, thereby increasing current density while managing the increased structural complexity through systematic fabrication processes.
Solution Approach 2:
The gate trench structure is nested within the drift region, with the gate electrode positioned inside the trench and surrounded by dielectric materials. This nested configuration allows the gate to control current flow through the drift region more effectively, enhancing on-state current density while maintaining breakdown voltage through the surrounding dielectric layers.
2Productivity
If higher current densities are achieved, then power handling improves, but breakdown voltage may be compromised
Solution Approach 1:
The patent applies different dielectric materials with different properties at different locations: a first dielectric material fills the gate trench providing gate control, while a second dielectric material is positioned at the trench edges providing field control and breakdown voltage enhancement. This local differentiation allows simultaneous optimization of current density and breakdown voltage.
Solution Approach 2:
The gate trench structure acts as an intermediary element between the gate electrode and the drift region, providing controlled electric field distribution. The dielectric materials within the trench mediate the electric field, allowing high current density when the transistor is on while maintaining high breakdown voltage when off, thus resolving the contradiction between current handling and voltage blocking capabilities.
3Productivity
If gate trench depth is increased, then on-state resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by forming the gate trench to a predetermined depth before final gate electrode deposition. The trench depth is carefully controlled during etching to ensure optimal electrical characteristics, and subsequent steps such as dielectric filling and planarization are performed to compensate for any variations, thereby reducing the impact of manufacturing precision limitations.
Solution Approach 2:
The patent optimizes the gate trench depth as a critical parameter to balance on-state resistance and manufacturing feasibility. By carefully selecting and controlling the trench depth parameter, along with other parameters such as dielectric layer thicknesses and doping concentrations, the patent achieves low on-state resistance while accommodating standard manufacturing precision capabilities.
Data Source
AI summary
An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.