Vertical MOS Gate Trench Layout for Lower On-Resistance
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Solution Overview
Problem
There is a demand for reducing the on-resistance of semiconductor devices that include a vertical MOS transistor and a peripheral element, as existing methods struggle to minimize on-resistance while maintaining breakdown voltage and photolithography precision.
Innovation Solution
A manufacturing method for a face-down mountable, chip-size-package semiconductor device that involves forming a semiconductor layer with a vertical MOS transistor and a peripheral element, where the peripheral element is made of polysilicon and is partially provided in a groove with a depth less than the gate trenches, allowing for chemical mechanical polishing to flush the surfaces and reduce the thickness of the polysilicon, thereby minimizing on-resistance and maintaining insulating properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the peripheral element is formed at the same level as gate trenches, then the manufacturing process is simpler, but the on-resistance cannot be reduced and photolithography precision deteriorates
Solution Approach 1:
The patent segments the groove formation into two distinct processes: first forming a shallow groove for the peripheral element, then forming deeper gate trenches. This segmentation allows the peripheral element to be positioned at a different level than the gate trenches, eliminating level differences in the resist application region and improving photolithography precision without significantly complicating the overall manufacturing process.
2Reliability
If the peripheral element thickness is increased, then the insulating property is improved, but the on-resistance increases
Solution Approach 1:
The patent applies local quality by positioning the peripheral element in a groove that does not extend to the semiconductor layer, creating a localized insulating structure. The peripheral element is formed only in the upper portion, providing sufficient insulation for protecting against surge current while minimizing the thickness to reduce on-resistance. This localized approach optimizes both insulating property and electrical performance.
3Manufacturing precision
If the groove depth is increased to reduce on-resistance, then the on-resistance is reduced, but the peripheral element cannot maintain sufficient insulating property
Solution Approach 1:
The patent solves this contradiction by transitioning to a three-dimensional structure where the peripheral element is positioned in a groove that is shallow relative to the gate trenches. This dimensional differentiation allows the peripheral element to maintain adequate thickness for insulating property while the gate trenches extend deeper to reduce on-resistance. The breakdown voltage is maintained through the peripheral element's positioning and the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the on-resistance of the vertical MOS transistor while maintaining a sufficient breakdown voltage and ensuring precise photolithography processing by eliminating level differences in the resist application region, allowing for narrower source regions and reduced mesa width.
Implementation Method 1
making a thickness of the peripheral element equal to the depth h by concurrently removing the polysilicon deposited in the plurality of gate trenches and the polysilicon deposited in the second groove by chemical mechanical polishing
Implementation Method 2
depositing a first oxide film up to at least the upper surface of the semiconductor layer to fill the first groove, and concurrently forming a second oxide film of a thickness a on the upper surface of the semiconductor layer and a third oxide film on an upper surface of the first oxide film
Data Source
AI summary
A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon; forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.