MOS Hysteresis Comparator Circuit Stability
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Solution Overview
Problem
Conventional MOS hysteresis comparators face challenges in maintaining a hysteresis characteristic that is unaffected by temperature and manufacturing process variations, due to increased area and power requirements, instability risks, and initial undefined states associated with existing bias circuit designs.
Innovation Solution
A MOS hysteresis comparator circuit that incorporates a hysteresis generating circuit to inject or draw a hysteresis current, depending on the output voltage, using a differential pair with matched transistors and a current source, which maintains a stable hysteresis characteristic without the need for error amplifiers or feedback loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a source transistor bias circuit is used to compensate for PVT variations, then the hysteresis voltage can be compensated, but the area and power requirements increase due to the need for an error amplifier
Solution Approach 1:
The patent extracts and removes the error amplifier and feedback loop components from the bias circuit, retaining only the essential source transistor biasing functionality. This eliminates the need for complex compensation mechanisms while maintaining hysteresis voltage stability through a simplified circuit topology.
Solution Approach 2:
The patent uses matched transistors (Q5 and Q6) to create a differential pair that inherently provides symmetry and stability. By copying the transistor characteristics and using them in a differential configuration, the circuit achieves PVT compensation without requiring additional active compensation components.
2Reliability
If a source transistor bias circuit with feedback loop is used, then PVT compensation is achieved, but instability risk increases
Solution Approach 1:
The patent eliminates the feedback loop entirely, using instead a direct biasing approach through the source transistor. The hysteresis effect itself provides the necessary stability through the cross-coupled transistors Q2 and Q3, making additional feedback mechanisms unnecessary and potentially harmful to stability.
3Reliability
If a source transistor bias circuit is used, then PVT compensation is possible, but start-up signal and circuitry are required due to initial undefined state
Solution Approach 1:
The patent designs the circuit with inherent asymmetry through the cross-coupled transistors Q2 and Q3, which automatically breaks the symmetry and establishes a defined initial state during startup. This preliminary structural design eliminates the need for external start-up signals or additional start-up circuitry.
4Reliability
If conventional MOS hysteresis comparator design is used, then hysteresis characteristic is achieved, but the design complexity increases and area requirements grow
Solution Approach 1:
The patent merges the hysteresis generation functionality directly into the comparator core structure by using cross-coupled transistors Q2 and Q3 that simultaneously provide both comparison and hysteresis functions. This integration eliminates separate hysteresis generation circuits and reduces overall complexity.
Data Source
AI summary
The present application relates to a hysteresis comparator, which comprises a hysteresis comparator circuit and a hysteresis generating circuit. The hysteresis comparator circuit two comparator legs each with a differential transistor and a load transistor. The differential transistors receive a comparator biasing current, which is variably divided based on the relative levels of the voltage signals applied to control terminals of the differential transistors. An output stage is provided for developing an output voltage signal based on currents flowing through the load transistors. The hysteresis generating circuit is arranged for selectively injecting a hysteresis current in or selectively drawing a hysteresis current from either one of the two comparator legs depending on the level of the output voltage signal.