MOS Image Sensor Peripheral Isolation Structure
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Solution Overview
Problem
MOS solid-state image pickup devices with voltage boosting circuits face issues of crosstalk and punch-through current due to the structure of their peripheral circuits, which affect image quality and efficiency.
Innovation Solution
The device incorporates a specific structure with an N-type semiconductor substrate, featuring a first P-type well for photodiodes, second P-type wells for N-Channel MOS transistors, and a third P-type well with higher impurity concentration to isolate the N-type well from the N-type epitaxial layer, preventing punch-through current and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage boosting circuit is provided to boost gate electrode voltages above external power supply voltage, then the sufficient number of saturated electrons is secured and residual image is prevented, but punch-through current occurs between the N-type well and N-type epitaxial layer
Solution Approach 1:
A third P-type well is introduced as an intermediary structure between the N-type well and N-type epitaxial layer. This intermediate P-type well prevents direct electrical contact between the N-type regions, thereby blocking the punch-through current path while allowing the voltage boosting circuit to function properly for residual image prevention.
Solution Approach 2:
The P-type well structure is segmented into multiple regions: a first P-type well containing photodiodes, second P-type wells for NMOS transistors, and a third P-type well specifically positioned to isolate the N-type well from the N-type epitaxial layer. This segmentation allows each P-type well region to serve its specific function while collectively solving the punch-through current problem.
2Productivity
If elements are reduced in size to decrease space occupation, then integration density is improved, but the sufficient number of saturated electrons cannot be secured in each photodiode
Solution Approach 1:
The diffusion layer is deeply formed by changing the diffusion depth parameter, extending the photodiode structure to greater depths. This increases the collection volume for charge carriers, allowing sufficient saturated electrons to be accumulated even when the photodiode surface area is reduced for higher integration density.
3Quantity of substance
If a diffusion layer is deeply formed to secure sufficient saturated electrons, then the number of saturated electrons is improved, but image signal charge cannot be entirely read due to low power supply voltage, causing residual image
Solution Approach 1:
The gate electrode voltages are made dynamic by providing a voltage boosting circuit that generates time-dependent voltage pulses exceeding the external power supply voltage. These boosted voltages are applied to transfer and reset transistors, enabling complete charge transfer and reset operations that prevent residual image while maintaining deep photodiode structures.
4Ease of manufacture
If peripheral circuits are formed near the pixel region using the same CMOS process, then manufacturing complexity is reduced, but crosstalk occurs between peripheral circuits and pixel region
Solution Approach 1:
The third P-type well is selectively formed only in the peripheral circuit region, creating a localized isolation structure. This allows the pixel region to maintain its standard structure for optimal performance while the peripheral circuit region gains additional isolation to prevent crosstalk, with each region having locally optimized properties.
Data Source
AI summary
An N-type epitaxial layer 115, which is formed above an N-type semiconductor substrate 114 in each of a pixel region and a peripheral circuit region; a first P-type well 1 formed above the N-type epitaxial layer 115 in the pixel region; and light receiving regions 117, which are formed within the first P-type well 1 and each of which is a component of a photodiode, are included. The peripheral circuit region includes: second P-type wells 2, which are formed from a surface 200 of the peripheral circuit region to a desired depth and each of which is a component of an N-Channel MOS transistor; an N-type well 3 which is formed from the surface 200 of the peripheral circuit region to a desired depth and which is a component of a P-Channel MOS transistor; and a third P-type well 4 which is formed so as to have such a shape as to isolate the N-type well 3 from the N-type epitaxial layer 115 and which has a higher impurity concentration than that of the first P-type well 1.