Unified MOS Testing Structure for Interface Trap Density
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Solution Overview
Problem
Conventional testing methods require separate structures and equipment for measuring interface trap density in n-type and p-type MOS devices, leading to time-consuming and costly processes with low efficiency.
Innovation Solution
A unified testing structure combining p-type and n-type MOS devices with a shared gate, utilizing a DC-IV scanning method to measure substrate current and determine interface trap density without additional process steps or equipment, eliminating the need for a pulse generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate testing structures are used for n-type and p-type MOS devices, then measurement completeness is improved, but measurement time and device complexity increase
Solution Approach 1:
The patent combines separate testing structures for n-type and p-type MOS devices into a single unified testing structure. The structure includes a first testing region for p-type devices and a second testing region for n-type devices, both sharing common components (gate electrode, gate oxide layer, substrate), enabling simultaneous measurement of both device types without requiring separate test setups.
Solution Approach 2:
The unified testing structure serves multiple functions by accommodating both n-type and p-type MOS device testing within the same physical structure. The common gate electrode and gate oxide layer can be used for testing both device types, making the structure universal and eliminating the need for separate specialized test structures.
2Measurement precision
If multiple separate testing structures are used, then comprehensive interface trap density information is obtained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges multiple testing structures into one unified structure that contains both p-type and n-type testing regions. This consolidation reduces the total number of separate structures needed while maintaining the capability to obtain comprehensive interface trap density information for both device types.
Solution Approach 2:
The testing structure is designed with universal components that serve both p-type and n-type device testing purposes. The common gate electrode, gate oxide layer, and substrate can be used for testing both device types, reducing manufacturing complexity and cost while providing complete interface trap density characterization.
3Measurement precision
If conventional testing methods with pulse generators are used, then measurement accuracy is maintained, but test equipment cost increases
Solution Approach 1:
The testing method utilizes the inherent electrical characteristics and existing circuit components of the MOS devices themselves to perform measurements. By applying voltages to the gate electrode and measuring currents through the devices, the system uses the devices' own properties for self-characterization, eliminating the need for external pulse generators and specialized test equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach integrates tests for both types into a single structure, reducing measurement time and cost, providing clear peak-based results that directly correlate with interface trap density, enhancing data analysis and eliminating the need for specialized test equipment.
Implementation Method 1
interface traps of the gate oxide layer decreases mobility of the device and degrades performance of the device
Data Source
AI summary
The present invention discloses a testing structure and method for interface trap density of gate oxide, relating to the field of quality and reliability researches of MOS devices. The present invention makes the interface traps density tests for gate oxide layers of n-type and p-type MOS devices completed on a same testing structure, this does not only shorten the measurement period by half but also decrease the costs for testing instruments, because the present testing method is based on a simple current-voltage scanning test without using equipments such as pulse generator required in conventional method. The testing results obtained according to the present invention are featured with spectral peak, which facilitates the data analysis and computation.