MOS Isolation With Dummy Gates and Continuous Active Areas
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Solution Overview
Problem
As MOS devices are miniaturized to the nanometer scale, they face challenges in maintaining operating speed and effective isolation due to limitations in shallow trench isolation (STI) and stressor size, leading to increased leakage current and power consumption.
Innovation Solution
Implementing a metal oxide semiconductor (MOS) isolation scheme with continuous active areas separated by dummy gates made from materials with opposite work functions, which reduces leakage current and enhances operating speed without the need for STI and additional power supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation (STI) is used to isolate active elements, then isolation between devices is improved, but valuable space within the IC is consumed and stressor dimensions are reduced
Solution Approach 1:
The patent extracts the isolation function from the traditional STI structure and relocates it to dummy gates positioned between active components. This allows the active area to remain continuous while isolation is provided by the dummy gates, thereby eliminating the space-consuming STI breaks and enabling larger stressor dimensions without compromising device isolation.
Solution Approach 2:
The patent introduces dummy gates as intermediary elements between active components. These dummy gates serve as mediators that provide electrical isolation between adjacent active areas while maintaining the continuity of the active region. The dummy gates fulfill the isolation function without requiring physical separation of the active areas, thus preserving space and enabling effective stressor formation.
2Speed
If stress inducing elements are made physically large to improve mobility, then current mechanism mobility is improved, but miniaturization goals are conflicted
Solution Approach 1:
The patent enables larger stressor dimensions by changing the spatial arrangement through continuous active areas. By removing STI breaks, the stressors can extend laterally across what would have been isolation regions, effectively utilizing the space in a different dimensional configuration. This allows stressors to achieve sufficient physical dimensions for effective mobility enhancement without increasing the overall device footprint.
3Area of stationary object
If dummy gates are used instead of STI breaks, then continuous active area is achieved, but isolation is worse and higher gate bias is required
Solution Approach 1:
The patent addresses the isolation quality issue by changing the electrical parameters of the dummy gates. By applying appropriate gate biases to the dummy gates, the electrical potential difference between adjacent active areas is controlled, thereby achieving effective electrical isolation. This parameter change allows the dummy gates to provide isolation comparable to or better than STI while maintaining continuous active areas.
4Area of stationary object
If MOS devices are miniaturized to nanometer scale, then footprint area is reduced, but operating speed does not improve due to mobility limitations
Solution Approach 1:
The patent changes the material parameters of the gate dielectric films by using high-k materials. This allows for thinner effective gate oxide equivalents while maintaining adequate electrical isolation and control. The high-k dielectric enables better electrostatic control in miniaturized devices, which improves carrier mobility and operating speed even as the device footprint is reduced to nanometer scale.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for further miniaturization and improved performance by reducing leakage current and increasing operating speed, while avoiding the limitations of STI and polygate technologies.
Implementation Method 1
The dummy gate is made from a material having an opposite work function relative to the gate material of the active area. For example, if the gate in the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.
Implementation Method 2
Unlike polygate MOS efforts, the gate dielectric films in certain embodiments disclosed herein have a relatively high dielectric constant (k), and thus allow reverse work function type dummy gates to provide the desired isolation while avoiding the need for an isolation implantation zone disposed underneath the dummy gate.
Data Source
AI summary
Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.