MOS Latch Power Glitch Detection for Security Chips
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Solution Overview
Problem
Existing power glitch signal detection circuits in security chips suffer from high power consumption, large area overhead, low reaction rate, low sensitivity, and poor portability due to their reliance on traditional RC sampling and comparator structures, making them vulnerable to fault attacks and inefficient in detecting nanosecond-level glitches.
Innovation Solution
A power glitch signal detection circuit utilizing a voltage sampling module with a MOS transistor and capacitor, eliminating the need for resistors, and incorporating a latch structure that reduces static bias current and hardware overhead, enabling high-speed, sensitive, and portable detection of power glitches on both power supply and ground voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If RC sampling structure with larger RC is used to detect nanosecond-level power glitch, then detection sensitivity is improved, but area overhead increases
Solution Approach 1:
The patent extracts and eliminates the resistor component from the traditional RC sampling structure, retaining only the capacitor element. This is achieved by using a latch circuit composed of cross-coupled inverters that can detect voltage changes without requiring a resistor, thereby reducing area overhead while maintaining detection sensitivity for nanosecond-level glitches.
Solution Approach 2:
The patent substitutes the passive RC electrical filtering mechanism with an active latch-based detection mechanism. The latch circuit uses positive feedback through cross-coupled inverters to amplify and hold the detected glitch signal, replacing the need for large RC time constants and thereby reducing the physical area required for detection.
2Measurement precision
If comparator structure with resistor divider is used to set decision threshold, then threshold accuracy is improved, but static bias power consumption increases
Solution Approach 1:
The patent removes the resistor divider and comparator components from the detection circuit, eliminating the source of static bias current. The threshold detection function is achieved inherently by the latch circuit's switching behavior, which responds to voltage changes without requiring continuous bias current flow through resistive dividers.
Solution Approach 2:
The latch circuit performs self-threshold detection through its inherent hysteresis and switching characteristics. The cross-coupled inverters automatically establish stable states based on the input voltage level, eliminating the need for external threshold-setting components that would consume static power.
3Reliability
If traditional RC sampling and comparator structure is used, then detection capability is achieved, but reaction rate decreases
Solution Approach 1:
The latch circuit operates with rapid switching transitions that respond instantaneously to voltage glitches. The cross-coupled inverters provide regenerative feedback that quickly amplifies small voltage changes into full logic level transitions, achieving fast reaction rates without the delay inherent in RC charging/discharging cycles.
Solution Approach 2:
The patent employs dynamic latch operation where the circuit transitions between stable states in response to glitch inputs. The cross-coupled inverters provide positive feedback that rapidly drives the circuit from one state to another, enabling fast response to nanosecond-level glitches without the speed limitations of passive RC circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves low power consumption, small area, high speed, high sensitivity, and strong portability, effectively detecting power glitches while reducing static power consumption and enhancing detection speed and sensitivity, thereby improving the robustness of security chips against fault attacks.
Implementation Method 1
a first metal oxide semiconductor MOS transistor and a capacitor for sampling a voltage of the power supply voltage
Implementation Method 2
a first metal oxide semiconductor MOS transistor and a capacitor for sampling a voltage of the power supply voltage, wherein a gate terminal of the first MOS transistor is connected to the capacitor
Data Source
AI summary
A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit includes a voltage sampling module, wherein the voltage sampling module includes: a first metal oxide semiconductor MOS transistor and a capacitor for sampling a power supply voltage, wherein a gate terminal of the first MOS transistor is connected to the capacitor, a source terminal of the first MOS transistor is connected to a ground voltage. The power glitch signal detection circuit further comprises a second MOS transistor and a signal output module. One terminal of the second MOS transistor is connected to a gate terminal of the first MOS transistor, another terminal of the second MOS transistor is connected to the power supply voltage, and a drain terminal of the second MOS transistor is connected to a drain terminal of the first MOS transistor.