3D Stacked Semiconductor Structure With MOS Layer Selectors
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Solution Overview
Problem
The challenge in fabricating 3D stacked semiconductor structures lies in scaling down the size while maintaining a narrow process window and implementing complex programming methods for PNVG structures, which are prone to channel potential leakage and require sophisticated operation waveforms.
Innovation Solution
A 3D stacked semiconductor structure is developed with a metal-oxide-semiconductor (MOS) layer formed between metal routes and stacking cells, comprising multi-layered pillars with insulating and conductive layers, and conductive plugs connected to MOS structures that function as layer-selectors for decoding and selecting the operational plane/layer, simplifying the fabrication and decoding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the 3D stacked semiconductor structure is scaled down, then storage capacity increases, but the process window becomes narrow
Solution Approach 1:
The invention divides the bit line structure into multiple independent bit line pads (102B, 103B, 104B, 105B) that are spatially segmented and independently formed. Each bit line pad serves a specific stack, allowing for independent fabrication and reducing the cumulative process complexity that would otherwise arise from scaling down the entire structure.
Solution Approach 2:
The invention transitions from a two-dimensional planar bit line structure to a three-dimensional stacked structure with bit line pads positioned at different vertical levels and horizontal locations. This dimensional expansion allows increased storage capacity while maintaining manufacturability through the use of standard semiconductor fabrication processes adapted for 3D stacking.
2Quantity of substance
If PNVG structure is used to achieve 3D stacking, then storage capacity increases, but reverse bias leakage and channel potential leakage occur
Solution Approach 1:
The invention extracts the problematic PN junction elements from the memory cell structure and replaces them with MOS-based selection mechanisms. By removing the P-type and N-type doped regions that cause reverse bias leakage, the structure achieves 3D stacking capability without the associated leakage problems.
Solution Approach 2:
The invention replaces complex, leakage-prone PNVG structures with simpler MOS transistor-based selection circuits that are easier to fabricate and control. The MOS structures provide sufficient layer selection functionality without requiring sophisticated operation waveforms or complex doping profiles.
3Ease of operation
If PNVG structure with sophisticated operation waveform is used, then layer selection is achieved, but device complexity increases
Solution Approach 1:
The invention replaces the complex electrical waveform control mechanism required for PNVG structures with a simpler MOS transistor switching mechanism. Instead of using sophisticated time-dependent voltage waveforms to achieve layer selection, the MOS structures provide intuitive voltage-controlled switching that is easier to implement and control.
4Reliability
If stairstep structures are used to connect semiconductor strips, then electrical coupling is achieved, but fabrication difficulty increases
Solution Approach 1:
The invention segments the bit line connections into discrete bit line pads (102B, 103B, 104B, 105B) that are independently formed and aligned with specific stacks. This segmentation simplifies the fabrication process by allowing each pad to be formed using standard photolithography and deposition techniques, rather than requiring complex stairstep formation processes.
Data Source
AI summary
A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of semiconductor layers arranged alternately. The MOS layer comprises a plurality of MOS structures connected to the conductive plugs respectively, and function as layer-selectors for selecting and decoding the to-be-operated layer.