MOS Transistor LDD Implant Layout With Selective Diffusion Suppression
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Solution Overview
Problem
As semiconductor devices advance with smaller critical dimensions, controlling implant profiles for both lightly doped drain (LDD) and non-LDD transistors on the same substrate becomes increasingly difficult, particularly when integrating complementary metal oxide semiconductor (CMOS) and analog devices with different performance metrics.
Innovation Solution
The approach involves forming a semiconductor device with a first transistor having a lightly doped drain (LDD) region and a diffusion suppressant region, and a second transistor without these regions, using a method that allows concurrent formation of source/drain regions, where a single photomask is used to differentiate between the two types of transistors through selective implantation and annealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate processing steps are used for LDD and non-LDD transistors, then device performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple separate processing steps into a single integrated process by performing LDD implantation and diffusion suppressant implantation in one combined step. This is accomplished by using a masking layer with selectively formed openings that expose different regions to the implant process simultaneously, thereby reducing the total number of processing steps while maintaining the ability to optimize performance for both LDD and non-LDD transistor types.
2Ease of manufacture
If a single implant profile is used for all transistors, then manufacturing simplicity is maintained, but control over implant profiles deteriorates
Solution Approach 1:
The patent introduces a masking layer as an intermediary element that enables precise control over implant profiles while maintaining process simplicity. The masking layer with selectively formed openings acts as a mediator between the single implant process and the different device requirements, allowing the implant process to deposit dopants uniformly while the mask selectively determines which regions receive the implantation, thereby achieving both simplicity and precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This strategy enables the integration of transistors with minimized diffusion for CMOS devices and increased diffusion for analog devices, meeting specific performance metrics by selectively adding a diffusion suppression region to one transistor while keeping the other free of such implants, thus optimizing performance and reducing complexity.
Implementation Method 1
a diffusion suppressant region with a diffusion suppressant species partially or completely overlapping the LDD region
Implementation Method 2
controlling implant profiles in semiconductor devices which contain both devices with lightly doped drain (LDD) implants and without LDD implants
Data Source
AI summary
The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.