MOS Transistor Leakage Testing for DDIC IO Yield Improvement
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Solution Overview
Problem
The existing methods for improving the yield of 8 V NMOS transistor devices in 28 nm display driver integrated circuit (DDIC) chips are inefficient, leading to increased development cycles and economic costs due to device leakage, which is often caused by trap charges resulting in excessive leakage currents.
Innovation Solution
A test method involving a series of voltage applications to MOS transistors, including gradual increases and reapplications of gate and drain voltages, with specific voltage ranges and steps, to detect and reduce leakage currents by eliminating trap electrons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical structure optimization is applied to improve device performance, then device leakage is reduced, but product development cycle increases and economic cost increases
Solution Approach 1:
The patent applies preliminary action by performing trap charge elimination through specific voltage stress treatment before final device testing and characterization. The method applies a series of gate and drain voltages in predetermined sequences (Steps I-IV) to proactively remove trap charges that would otherwise cause leakage issues, thereby eliminating the need for iterative physical structure optimizations and reducing development cycle time
2Reliability
If physical structure optimization is applied to improve device performance, then device leakage is reduced, but economic cost increases
Solution Approach 1:
The patent applies parameter changes by modifying electrical operating parameters (gate voltage from -2V to 8V, drain voltage from 0V to 14V) to achieve trap charge elimination and leakage reduction. This electrical parameter-based approach replaces costly physical structure modifications, maintaining ease of manufacture while improving device reliability
3Reliability
If breakdown voltage current test is applied to improve device performance, then some improvement is achieved, but the improvement effect is non-significant
Solution Approach 1:
The patent applies periodic action by implementing a structured four-step voltage stress sequence with specific timing and voltage levels. The method periodically applies gate voltages (-2V to 8V) and drain voltages (0V to 14V) in controlled cycles, which systematically eliminates trap charges more effectively than continuous breakdown voltage testing, significantly improving productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces leakage currents by two orders of magnitude, improving product yield and reducing power consumption, by continuously applying currents to eliminate trap electrons in the device structure.
Implementation Method 1
applying a current to the drain of the device at a breakdown voltage only leads to a non-significant improvement effect or no improvement effect. Accordingly, it is necessary to propose a new method to solve the above problem from such IO device leakage current which is the cause of a low yield.
Implementation Method 2
by applying a current effect to the drain of the IO device, the present application restricts a current to act on the IO device continuously, which may effectively eliminate the possible presence of trap electrons in the structure and reduce the leakage current of the IO device
Data Source
AI summary
The present application discloses a device leakage current test method. The method includes: applying a gradually increasing first gate voltage within a range to a gate of the MOS transistor; applying a first drain voltage to a drain of the MOS transistor; reapplying a gradually increasing second gate voltage within a range to the gate of the MOS transistor; reapplying a second drain voltage to the drain of the MOS transistor; reapplying a gradually increasing third drain voltage in a range to the drain of the MOS transistor; detecting a variation of the drain current as the first leakage current; and reapplying a gradually increasing fourth drain voltage to the drain of the MOS transistor, with a step of 0.04 V and a variation range; and detecting a variation of the drain current as the second leakage current.