MOS Interconnect Layout Using LIL to Cut Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional MOS devices experience undesirable parasitic capacitance between drain and source terminals due to the adjacent configuration of metal-1 layer strips, which affects the device's performance.
Innovation Solution
The introduction of a plurality of local interconnect layers (LIL) in the MOS device, which are connected to the source and drain terminals, is used to reduce the overlap of metal-1 layer strips between these terminals, thereby minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal-1 layer strips are configured adjacent to each other to connect source and drain terminals, then the device structure is simple and easy to manufacture, but parasitic capacitance between drain and source terminals increases
Solution Approach 1:
The invention divides the connection path between source and drain terminals into multiple segments by introducing local interconnect layers (LIL). Instead of using a single continuous metal-1 layer, the connection is segmented through multiple LIL layers that are selectively positioned, allowing the metal-1 strips to be separated and avoiding their direct adjacency, thus reducing parasitic capacitance while maintaining manufacturability.
Solution Approach 2:
The invention transitions from a two-dimensional planar arrangement of metal-1 layers to a three-dimensional stacked configuration by introducing local interconnect layers at different vertical levels. This dimensional change allows source and drain connections to be routed through different layers, preventing the metal-1 strips from being adjacent in the planar view and thereby reducing parasitic capacitance between them.
2Object-generated harmful factors
If metal-1 layer strips are placed adjacent to reduce parasitic capacitance, then parasitic capacitance decreases, but device complexity increases
Solution Approach 1:
The invention introduces local interconnect layers (LIL) as intermediary elements between the source and drain terminals. These LIL layers act as mediators that connect to the metal-1 layers at specific points, allowing the metal-1 strips to be separated and reducing parasitic capacitance. The LIL serves as an intermediate connection structure that manages the complexity by providing a systematic way to route connections without direct metal-1 adjacency.
Data Source
AI summary
A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias. A plurality of local interconnect layers, LIL, (470) are connected respectively to the least one source terminal and at least one drain terminal through the number of respective contact vias, wherein the at least one source terminal and the at least one drain terminal respectively connected to the plurality of LIL (470) are configured such that: the at least one source terminal and the at least one drain terminal do not overlap in a first direction (602) and a second direction (604) that is orthogonal to the first direction (602); and the at least one source terminal and the at least one drain terminal do not overlap or only a proportion of the at least one source terminal and the at least one drain terminal overlap in a third direction (606), where the third direction (606) is orthogonal to both the first direction (602) and the second direction (604).