Multi-Terminal MOS Device Model for LVS Accuracy
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Solution Overview
Problem
Current four-terminal MOS device models cannot accurately describe the electrical characteristics of n-type MOS devices with deep n-type wells used in high voltage applications, leading to difficulties in design stages like SPICE simulation and LVS check, as they do not account for the additional terminals from face-to-face diodes, resulting in a need for a more comprehensive multi-terminal MOS device model.
Innovation Solution
A multi-terminal MOS device model is developed, incorporating all possible combinations of deep n-type wells and breakdown voltages, and a four-terminal MOS device model with an isolation ring is used to reduce the number of required models, employing a dummy device like a metal resistor between body contact terminals to differentiate voltage potential swaps during LVS checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated multi-terminal MOS device model is developed to accurately describe electrical characteristics of n-type MOS devices with deep n-type wells, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the multi-terminal MOS device model into a standard four-terminal MOS device model plus separate diode models for the face-to-face diodes. This segmentation allows the complex multi-terminal behavior to be described by combining simpler, well-understood models, reducing the need for entirely new complex models while maintaining accuracy in describing electrical characteristics including breakdown voltages.
Solution Approach 2:
The patent creates a universal modeling approach that can handle both standard four-terminal MOS devices and multi-terminal MOS devices with deep n-type wells using a unified framework. The same four-terminal MOS device model combined with diode models can describe various device configurations (different breakdown voltages, different well structures) without requiring separate dedicated models for each case, thus reducing the total number of models needed.
2Adaptability or versatility
If a multi-terminal MOS device model including all combinations of deep n-type wells and breakdown voltages is developed, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the device variations into independent parameters (MOS device parameters and diode parameters) that can be independently selected and combined. This allows the model library to cover all combinations of deep n-type wells and breakdown voltages by mixing and matching standard MOS models with appropriate diode models, rather than creating separate models for each combination, thus maintaining adaptability while reducing complexity.
Solution Approach 2:
The patent develops a universal modeling framework that can accommodate any combination of MOS device types and diode configurations through a single unified approach. The same basic four-terminal MOS device model combined with standard diode models can represent all device variations in the foundry's semiconductor process, providing universal adaptability without requiring 300 separate dedicated models.
3Device complexity
If a four-terminal MOS device model with isolation ring is used to reduce the number of required models, then device complexity is reduced, but measurement precision may be affected
Solution Approach 1:
The patent introduces a dummy device (isolation ring) as an intermediary element between the body contact terminals. This dummy device acts as a mediator that enables the LVS tool to differentiate between different voltage potentials without requiring complex multi-terminal models. The isolation ring serves as a physical and modeling intermediary that resolves the ambiguity in voltage potential identification while keeping the model library simple.
Solution Approach 2:
The patent changes the modeling parameter approach by using the presence and configuration of the isolation ring (dummy device) as a distinguishing parameter. Instead of relying on complex multi-terminal models to differentiate voltage potentials, the approach uses the isolation ring's electrical characteristics (resistance, capacitance) as identifiable parameters that the LVS tool can detect and use to distinguish between different terminal connections, maintaining measurement precision while reducing model complexity.
Data Source
AI summary
A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.