MOS/MOM Sub-Pixel Capacitor Structure for High-Resolution Displays
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Solution Overview
Problem
Existing display technologies face challenges in achieving high-resolution panels due to limitations in sub-pixel design, particularly in the capacitive components, which affect the processing time and capacity, hindering the development of advanced display devices like head-mounted displays for virtual and augmented reality.
Innovation Solution
The implementation of a sub-pixel design that incorporates a first capacitor as a metal-oxide-semiconductor (MOS) capacitor and a second capacitor as a metal-oxide-metal (MOM) capacitor, with the first capacitor having a higher capacity than the second, and both capacitors being formed on different layers, along with specific transistor configurations to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional capacitor designs are used in sub-pixels, then manufacturing is simpler, but processing time is too long and capacity is insufficient for high-resolution panels
Solution Approach 1:
The capacitor system is segmented into two distinct capacitors (first capacitor and second capacitor) with different structures and functions. The first capacitor uses a planar parallel plate structure for basic charge storage, while the second capacitor employs a folded electrode structure to increase capacitance density. This segmentation allows each capacitor to be optimized for its specific function, reducing overall processing time while maintaining sufficient capacity.
Solution Approach 2:
The second capacitor introduces a three-dimensional folded electrode structure instead of traditional planar configuration. By folding the electrodes multiple times within a compact space, the effective capacitance area is dramatically increased without proportionally increasing the footprint area. This dimensional transformation enables higher capacity in a constrained sub-pixel area, solving the capacity limitation for high-resolution displays.
2Quantity of substance
If capacitor capacity is increased for high-resolution panels, then sufficient charge storage is achieved, but processing time becomes excessively long
Solution Approach 1:
The total capacitance requirement is segmented between two capacitors with different capacity characteristics. The first capacitor provides baseline capacity with fast charging characteristics due to its simple planar structure. The second capacitor supplements the total capacity with its folded electrode design, which achieves high capacitance in a compact form. This segmentation enables sufficient total capacity without requiring a single large-capacity capacitor that would increase processing time.
Solution Approach 2:
The capacitor system combines two different capacitor architectures (planar parallel plate and folded electrode) into a composite structure. Each capacitor type contributes different electrical characteristics - the planar structure offers fast response and simple manufacturing, while the folded structure provides high capacitance density. This composite approach achieves optimal balance between capacity and processing speed that neither structure could achieve alone.
3Manufacturing precision
If sub-pixel design is optimized for high-resolution panels, then display quality improves, but manufacturing complexity increases
Solution Approach 1:
The complex capacitor requirements are segmented into two manageable structures that can be manufactured using different process complexities. The first capacitor uses a simple planar structure compatible with standard manufacturing processes. The second capacitor uses a folded electrode structure that, while more complex, is still fabricable using established thin-film deposition and patterning techniques. This segmentation allows high-resolution performance to be achieved without requiring entirely new manufacturing capabilities.
Solution Approach 2:
The folded electrode structure transforms a two-dimensional planar capacitor into a three-dimensional configuration, achieving high capacitance in a compact footprint suitable for high-resolution sub-pixels. This dimensional transformation allows the sub-pixel to maintain small size for high resolution while incorporating sufficient capacitance through vertical space utilization in the folded structure, without requiring proportionally larger manufacturing areas.
Data Source
AI summary
A sub-pixel includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor that is connected between a data line and the third node, wherein a gate electrode of the second transistor is connected to a first sub-gate line; a first capacitor connected between the first node and the third node; and a second capacitor connected between the second node and the third node, wherein the first capacitor and the second capacitor are formed as different types of capacitors.