MOS Device Offset Spacer Formation via Selective Etching
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Solution Overview
Problem
Conventional methods for forming dielectric offset spacers in MOS devices face challenges in controlling etching processes, leading to damage of gate oxide and silicon loss due to plasma charging and inadequate control of critical dimensions as device sizes scale below 0.13 microns.
Innovation Solution
A method involving a dielectric stack with a first silicon oxide layer, a second silicon nitride layer, a third silicon oxide layer, and a fourth silicon nitride layer is used, where a plasma etching process removes the top silicon nitride layer, followed by wet etching processes using diluted hydrofluoric acid and sulfuric peroxide mixtures to form an offset spacer, maintaining the profile of the bottom silicon oxide layer and preventing silicon loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a dry etching process is used to remove deposited silicon oxide or silicon nitride layers for offset spacer formation, then the offset spacer can be formed, but plasma charging damages the gate oxide underneath and induces silicon loss in the substrate
Solution Approach 1:
The patent segments the etching process into multiple selective etching steps, each targeting a specific dielectric layer (first silicon oxide layer, second silicon nitride layer, third silicon oxide layer) with different etching conditions and selectivities. This segmentation allows precise control over which layers are removed and protects the gate oxide from plasma charging damage by using wet etching for the final offset spacer formation step.
Solution Approach 2:
The patent changes the etching parameters by switching from dry plasma etching to wet chemical etching for the critical offset spacer formation step. This parameter change eliminates plasma charging effects that cause gate oxide damage and silicon loss, while still achieving the desired offset spacer structure through controlled chemical etching of the third silicon oxide layer.
2Productivity
If device characteristic sizes are scaled below 0.13 microns, then device density and performance are improved, but the process window for wet and dry etching processes becomes increasingly difficult to control to achieve desired critical dimensions
Solution Approach 1:
The patent divides the dielectric stack into multiple layers with different materials and thicknesses, allowing selective removal of each layer through targeted etching processes. This segmentation enables precise control of critical dimensions at scaled sizes by independently optimizing the etching conditions for each layer, achieving the desired offset spacer width even in sub-0.13 micron devices.
Solution Approach 2:
The patent applies different etching selectivities to different regions and layers of the dielectric stack. By using wet etching with specific chemical compositions for the third silicon oxide layer removal, the process achieves high precision in offset spacer width control while maintaining the integrity of underlying layers, enabling accurate critical dimension control at scaled device sizes.
3Ease of manufacture
If a single silicon oxide layer or composite layer is deposited and then portions are removed by dry etching, then offset spacer formation is achieved, but the gate oxide underneath is damaged and silicon loss occurs in the substrate
Solution Approach 1:
The patent changes the chemical and physical parameters of the etching process by using wet chemical etching instead of dry plasma etching for the offset spacer formation step. This parameter change eliminates the harmful plasma charging effects that damage gate oxide and cause silicon loss, while still achieving effective offset spacer formation through controlled chemical removal of the third silicon oxide layer.
Solution Approach 2:
The patent introduces a multi-layer dielectric structure with alternating silicon oxide and silicon nitride layers as intermediaries. The third silicon oxide layer serves as a sacrificial intermediate layer that can be selectively removed by wet etching to form the offset spacer, while the underlying gate oxide is protected from direct exposure to aggressive etching chemicals through the protective nitride layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively forms an offset spacer around the gate structure while protecting the gate insulating layer and preventing silicon loss, enabling precise control of critical dimensions and improving the fabrication process for MOS devices.
Implementation Method 1
the removal of portions of the deposited silicon oxide or silicon nitride layers is usually accomplished by a dry etching process, such as a plasma etching
Implementation Method 2
plasma charging from the dry etching process not only penetrates the gate electrode to damage the gate oxide underneath
Implementation Method 3
performing a second wet etching process using diluted hydrofluoric acid for removing a portion of the third dielectric layer
Implementation Method 4
performing a third wet etching process using sulfuric peroxide mixtures for removing a portion of the second dielectric layer
Data Source
AI summary
A method for forming an offset spacer of a MOS device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a dielectric stack on the substrate and the gate structure, wherein the dielectric stack includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer; and performing an etching process on the dielectric stack to form an offset spacer around the gate structure.