Active MOS Overvoltage Limiting for DC-DC Converter Inputs
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Solution Overview
Problem
Switched-mode power supply devices experience reliability issues due to overvoltages caused by stray inductances in the package, leading to accelerated degradation of MOS transistors and electromagnetic interference (EMI) due to resonant circuits formed by decoupling capacitors and parasitic inductances.
Innovation Solution
An active voltage limiting circuit is introduced, comprising a MOS transistor that automatically switches to a conducting state when an overvoltage is detected, using a capacitive divider for fast triggering and a cascoded transistor to minimize snapback risk, thereby reducing the overvoltage to a manageable level and damping oscillations to prevent EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are used to address overvoltage, then overvoltage protection is provided, but the device occupies more silicon area and can cause electromagnetic interference through resonant circuits
Solution Approach 1:
The patent changes the operational parameters of the MOS transistor by applying a gate voltage that varies based on the detected overvoltage condition. When overvoltage is detected, the gate voltage is adjusted to modify the transistor's channel conductivity, thereby limiting the overvoltage effect dynamically rather than using static decoupling capacitors.
Solution Approach 2:
The patent replaces the passive mechanical/electrical system of decoupling capacitors with an active electronic control system using MOS transistors and control circuitry. This substitution allows for dynamic response to overvoltage conditions while occupying less silicon area and avoiding resonant circuit issues.
2Reliability
If decoupling capacitors are used to address overvoltage, then overvoltage protection is provided, but electromagnetic interference is generated due to resonant circuits
Solution Approach 1:
The patent replaces the passive resonant circuit formed by decoupling capacitors and parasitic inductances with an active MOS transistor-based voltage limiting circuit. This active circuit responds dynamically to overvoltage conditions without forming resonant circuits, thereby eliminating the source of electromagnetic interference while maintaining protection functionality.
Solution Approach 2:
The patent converts the potentially harmful effect of parasitic inductances (which cause resonance with decoupling capacitors) into a controlled situation by using MOS transistors to actively limit voltage. The control circuit detects overvoltage caused by parasitic inductances and responds by modifying transistor conductivity, transforming the harmful resonant effect into a controlled voltage limitation without EMI.
3Area of stationary object
If an active voltage limiting circuit is used instead of decoupling capacitors, then silicon area is reduced and EMI is minimized, but circuit complexity increases
Solution Approach 1:
The patent merges the voltage limiting function with the existing power supply input circuitry by integrating MOS transistors directly at the input pads. The control circuit for detecting overvoltage and activating the limiting function is combined with the power supply interface, creating a unified structure that reduces overall circuit complexity despite the active components involved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The active voltage limiting circuit effectively reduces overvoltage peaks, enhancing the reliability of MOS transistors and minimizing EMI, while requiring less silicon space compared to traditional decoupling capacitors.
Implementation Method 1
using a capacitive divider for fast triggering
Implementation Method 2
comprising a MOS transistor that automatically switches to a conducting state when an overvoltage is detected
Implementation Method 3
and a cascoded transistor to minimize snapback risk
Data Source
AI summary
A voltage limiting circuit is provided. An example voltage limiting circuit comprises a first terminal capable of receiving a first supply voltage from a first initial voltage by means of a first path at least inductive, a second terminal capable of receiving a second supply voltage from a second initial voltage by means of a second path at least inductive, the voltage difference between the two terminals being likely to have an overvoltage, a first MOS transistor having a drain and a source respectively connected to two terminals and control means, triggerable by the overvoltage itself and configured to automatically switch the first MOS transistor to a conducting state when the overvoltage reaches a first value and to limit the overvoltage to a second value higher than the first value.