Vertical MOS Semiconductor Package Anchoring for Substrate Embedding
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Solution Overview
Problem
There is a demand for reducing the space required by mounting substrates for semiconductor devices, and existing methods do not effectively stabilize the position of semiconductor devices embedded in such substrates during mounting.
Innovation Solution
A semiconductor device with a chip-size-package structure, featuring copper wiring electrodes and protective film openings, includes perimeter structures that protrude to anchor the device in the mounting substrate, allowing for accurate processing and stabilization during embedding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a mounting method embedding semiconductor devices in mounting substrates is used to reduce mounting substrate space, then the area of the mounting substrate is reduced, but the position stability of the semiconductor device during mounting deteriorates
Solution Approach 1:
The patent applies preliminary action by forming protruding perimeter structures on the semiconductor device before mounting. These structures protrude from the surface of the semiconductor device and serve as anchors that are inserted into the mounting substrate during the embedding process, pre-establishing position stability before the actual mounting occurs.
Solution Approach 2:
The patent applies segmentation by dividing the mounting interface into distinct functional regions: the protruding perimeter structures that provide mechanical anchoring, the semiconductor device body, and the mounting substrate. This segmentation allows each component to be optimized independently for its specific function while working together as a integrated system.
2Stability of the object's composition
If protruding perimeter structures are added to stabilize the semiconductor device position, then the position stability is improved, but the device complexity increases
Solution Approach 1:
The patent applies merging by combining the protruding perimeter structures with the existing copper wiring electrodes and protective film openings. The perimeter structures are formed by stacking these existing components, thereby achieving position stabilization without adding separate complex structures, as the stabilization features are integrated into the existing device architecture.
Solution Approach 2:
The patent applies multi-functionality by designing the perimeter structures to serve multiple functions simultaneously: they provide mechanical anchoring for position stability, maintain electrical insulation through the protective film, and preserve copper wiring connectivity. This multi-functionality reduces the need for additional dedicated components.
3Reliability
If copper wiring electrodes are used to thoroughly cover exposed portions of source and gate electrodes, then the electrical conductivity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by utilizing the inherent material properties of copper, specifically its high electrical conductivity and ductility. The copper wiring electrodes are deposited to thoroughly cover the exposed portions of source and gate electrodes, and their material parameters enable reliable electrical connection even with variations in coverage thickness, thereby reducing the stringency of manufacturing precision requirements.
Solution Approach 2:
The patent applies composite materials by creating a multi-layer structure where copper wiring electrodes are stacked over the semiconductor electrodes. This composite structure combines the high conductivity of copper with the underlying semiconductor materials, achieving reliable electrical connection while the layered composite nature provides tolerance for manufacturing variations in each individual layer.
Data Source
AI summary
A semiconductor device includes: a semiconductor layer; a vertical metal-oxide semiconductor (MOS) transistor; a protective film; a first wiring electrode connected to a source electrode of the vertical MOS transistor; and a second wiring electrode connected to a gate electrode of the vertical MOS transistor. A first perimeter structure is provided in a perimeter portion of the first wiring electrode in the plan view of the semiconductor layer, the first perimeter structure protruding upward of the semiconductor device and including the source electrode, the protective film, and the first wiring electrode that are stacked in stated order. A second perimeter structure is provided in a perimeter portion of the second wiring electrode in the plan view of the semiconductor layer, the second perimeter structure protruding upward of the semiconductor device and including the gate electrode, the protective film, and the second wiring electrode that are stacked in stated order.