MOS Pair Layout Architecture for Uniform Gate Line Width
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Solution Overview
Problem
The increasing complexity of integrated circuits due to down-scaling leads to restricted design rules that cause increased chip area usage, difficulty in auto placement and routing, and design rule violations, particularly in small-scale integrated circuits where twisted polysilicon lines result in critical dimension variations and non-uniform line widths.
Innovation Solution
The layout of PMOS and NMOS transistors is optimized by placing the interconnection port outside the MOS pair region, using a substantially straight gate electrode strip with uniform width, and parallel gate length directions, along with parallel metal lines connecting drain regions, to avoid design rule violations and improve line uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If twisted polysilicon lines are used in conventional layouts, then the layout can be formed, but critical dimension variations occur and chip area increases
Solution Approach 1:
The patent inverts the conventional approach by moving the interconnection port from the interior to the exterior of the MOS pair region. This reversal eliminates the need for twisted polysilicon lines to reach the port, thereby achieving uniform line widths and consistent critical dimensions without increasing chip area
2Ease of operation
If interconnection port is placed inside MOS pair region, then routing is simplified, but design rule violations occur and line width uniformity deteriorates
Solution Approach 1:
The patent resolves the contradiction by changing the spatial dimension of the interconnection port placement from inside to outside the MOS pair region. This dimensional repositioning allows the gate polysilicon line to maintain uniform width while still achieving effective routing connection, thus satisfying both design rules and manufacturing precision requirements
3Manufacturing precision
If poly jog is used to fix line width uniformity, then line width can be improved, but design rules are violated
Solution Approach 1:
The patent extracts the interconnection port from the MOS pair region interior and places it on the exterior. This extraction eliminates the need for poly jog modifications, thereby maintaining both line width uniformity and design rule compliance simultaneously without requiring corrective measures
4Reliability
If M2 routing is used to connect drains, then design rules are satisfied, but M2 usage rate increases
Solution Approach 1:
The patent performs preliminary action by strategically positioning the interconnection port on the exterior of the MOS pair region before routing connections are made. This advance placement enables direct M1 routing to the port without requiring additional M2 layers, thus satisfying design rules while minimizing metal usage
Data Source
AI summary
An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.