Multi-Line MOS Power Supply Circuit for Low-Standby Semiconductors
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Solution Overview
Problem
There is a demand for reducing standby power consumption in semiconductor devices and systems, particularly in applications like keyless entry systems in vehicles, where existing technologies have limitations in achieving low power consumption.
Innovation Solution
The semiconductor device includes a first and second power supply voltage line, first and second reference voltage lines, impedance elements, and MOS transistors connected in series between the power supply and reference voltage lines. This configuration reduces the amplitude of the clock signal supplied to the logic circuit, thereby reducing the dark current and achieving low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional power supply configuration is used, then power supply stability is maintained, but standby power consumption is high
Solution Approach 1:
The power supply system is segmented into multiple independent voltage lines (first power supply voltage line, second power supply voltage line, first reference voltage line, second reference voltage line) with impedance elements between them. This segmentation allows selective power distribution and reduces unnecessary power consumption in standby mode while maintaining stability through the distributed voltage lines.
Solution Approach 2:
Impedance elements are introduced as intermediary components between the power supply voltage lines and reference voltage lines. These impedance elements control current flow and voltage distribution, enabling reduced power consumption in standby mode while maintaining power supply stability through controlled impedance matching.
2Productivity
If clock signal amplitude is increased, then logic circuit performance is improved, but dark current increases
Solution Approach 1:
Different voltage levels are applied to different parts of the logic circuit through the multi-line power supply configuration. The first and second power supply voltage lines provide different voltage levels to different circuit blocks, allowing optimization of clock signal amplitude locally to reduce dark current while maintaining overall circuit performance.
Solution Approach 2:
The patent changes the voltage parameters by introducing multiple power supply voltage lines with different voltage levels and multiple reference voltage lines. This parameter variation allows optimization of the clock signal amplitude to reduce dark current while maintaining logic circuit performance through controlled voltage differences.
Data Source
AI summary
A semiconductor device includes a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing a predetermined processing on an input signal, and provided in series between the second power supply voltage line and the second reference voltage line, and having gates connected to drains, a first transistor which is a P-channel MOS transistor, and a second transistor which is an N-channel MOS transistor.