MOS PUF Current Comparison Using Fixed-Gate Diode Transistors
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Solution Overview
Problem
Existing physically unclonable functions (PUFs) in integrated circuits are sensitive to temperature changes and aging, and require modifications to conventional CMOS processes, making them less robust and detectable.
Innovation Solution
A PUF device based on diode-connected MOS transistors with a random distribution of threshold voltages, where a group of transistors defines a reference current and others generate a digital output code, with fixed gate voltages and structurally identical branches to reduce variability and sensitivity to aging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diode-connected transistors with random threshold voltage distribution are used to create PUF, then the PUF becomes difficult to detect and robust against temperature variations and aging, but it requires modifications to conventional CMOS processes
Solution Approach 1:
The patent changes the operating parameters of standard CMOS transistors by connecting them in diode configuration (gate connected to drain) and operating them in weak inversion mode. This parameter change enables the transistors to exhibit strong threshold voltage variability without requiring any modifications to the CMOS fabrication process itself, thus achieving both reliability and ease of manufacture
Solution Approach 2:
The patent uses standard CMOS transistors that serve multiple functions: they can be used in conventional digital circuitry when needed, and can be reconfigured as diode-connected PUF elements when security features are required. This multi-functionality eliminates the need for separate PUF-specific transistor structures or process modifications
2Manufacturing precision
If diode-connected transistors are used in PUF, then variability is reduced to mainly threshold voltages, but other parameters such as PMOS NMOS diodes remain difficult to control
Solution Approach 1:
The patent extracts and eliminates the problematic diode formation mechanism by using only NMOS transistors in the PUF array, removing the PMOS-NMOS diode interface that causes uncontrolled variability. The design focuses exclusively on controlling NMOS threshold voltage distribution, simplifying the parameter control landscape
Solution Approach 2:
The patent applies different design treatments to different parts of the transistor structure: the channel region is optimized for threshold voltage control through careful dimensioning and biasing, while the source and drain regions are designed with extended layouts to minimize variability. This local quality approach ensures that each region contributes optimally to the overall PUF performance
3Reliability
If a large number of transistors are used to define the PUF code, then the code uniqueness and unpredictability improve, but the device area and complexity increase
Solution Approach 1:
The patent employs dynamic biasing schemes where the gate-source voltage of each transistor is independently controlled and adjusted. This dynamic control allows the system to optimize the effective number of bits from a fixed transistor array, achieving high code uniqueness without proportionally increasing the physical device area
Solution Approach 2:
The patent implements a hierarchical structure where transistors are arranged in arrays with shared control circuits and readout logic. Multiple transistors share common biasing and measurement infrastructure, allowing the PUF code length to scale without linearly increasing the overall device area, similar to nested dolls where smaller components are contained within larger structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the robustness and detectability of PUFs by minimizing variability to threshold voltages, maintaining robustness against temperature changes and aging, while being producible using conventional CMOS methods.
Implementation Method 1
the implantations of dopants leading to implanted source and drain regions having unpredictable characteristics that are different from one transistor to another
Data Source
AI summary
The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.