N-Channel MOS Pulse Output Circuit Without Embedded Regulators
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Solution Overview
Problem
Existing semiconductor devices require embedded regulators with large internal capacity or high speed to drive high-speed and large-current pulse transmission, leading to increased element area, voltage range issues, and the need for level shifters, making them difficult to mount and operate efficiently.
Innovation Solution
A semiconductor device using N channel MOS transistors with inserted load and source resistances, powered externally without an embedded regulator, eliminating the need for level shifters and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an embedded regulator is used to drive high-speed and large-current pulse transmission, then the transmission performance is improved, but the element area increases and the device becomes difficult to mount
Solution Approach 1:
The regulator function is extracted from the embedded configuration and moved to an external power supply. This removes the large internal capacity regulator from the chip, reducing element area while maintaining the ability to drive high-speed and large-current pulses through the N channel MOS transistor output stage
2Power
If an embedded regulator with large internal capacity is used, then the power supply capability is improved, but the voltage range becomes restricted and device complexity increases
Solution Approach 1:
The regulator is extracted from the device and placed externally, reducing internal device complexity. The external power supply handles voltage regulation, allowing the internal circuit to focus on high-speed pulse transmission functionality
Solution Approach 2:
The external power supply serves multiple functions: voltage regulation, current supply, and adaptation to different voltage ranges. This multi-functional approach replaces the specialized embedded regulator, reducing device complexity while maintaining power supply capability
3Adaptability or versatility
If a level shifter circuit is added to convert low voltage signal to high voltage signal, then the voltage compatibility is improved, but the operation speed decreases and device complexity increases
Solution Approach 1:
The level shifting function is extracted from the signal path and handled by the external power supply and circuit configuration. This removes the level shifter circuit from the high-speed signal path, preserving operation speed while maintaining voltage compatibility through the N channel MOS transistor's inherent voltage handling capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed and large-current pulse output without requiring embedded regulators, reducing power consumption and avoiding the need for level shifters, thus allowing efficient operation and compact design.
Implementation Method 1
a semiconductor device which outputs a high-speed and large-current pulse using an N channel MOS transistor
Data Source
AI summary
A semiconductor device that outputs a high-speed and large-current pulse is provided. The semiconductor device includes: a first N channel transistor having its gate receiving a second voltage as its input; a first resistance element having its second terminal connected to a drain of the first N channel transistor; a second resistance element having its first terminal connected to a source of the first N channel transistor; a second N channel transistor having its gate receiving a second voltage as its input; a third resistance element having its second terminal connected to a drain of the second N channel transistor; a fourth resistance element having its first terminal connected to a source of the second N channel transistor; and an isolator having its first terminal connected to the drain of the first N channel transistor and having its second terminal connected to the drain of the second N channel transistor.


