MOS Devices with Raised Source/Drain Stressors

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Solution Overview

Problem

The formation of raised source/drains in integrated circuits is challenging due to losses in source/drain regions caused by cleaning processes, which existing epitaxial growth methods struggle to compensate effectively.

Innovation Solution

The method involves forming silicon germanium stressors and simultaneously growing silicon layers using epitaxy, with p-type impurities doped in-situ, to introduce tensile stress and improve drive current in NMOS devices, reducing the need for additional masking and process steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If epitaxial growth is used to compensate for source/drain region loss, then the drive current is improved, but the manufacturing process complexity increases

Engineering Contradiction:
Improvedrive currentVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the formation of silicon germanium stressors and the growth of silicon layers into a single simultaneous epitaxial growth process. This merging of operations compensates for source/drain region loss while introducing tensile stress to improve drive current, all without requiring separate process steps or additional masking in PMOS regions, thereby improving reliability while avoiding increased manufacturing complexity

Inventive Principle:
Principle #5Merging (Combining)

2Manufacturing precision

If separate masking steps are performed for PMOS regions, then the manufacturing precision is improved, but the productivity decreases

Engineering Contradiction:
Improvepattern alignment precisionVSAvoidmanufacturing throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent extracts and eliminates the separate masking step for PMOS regions from the manufacturing process. By using simultaneous epitaxial growth that inherently provides selective stressor formation and silicon layer growth, the process achieves the necessary pattern alignment precision without requiring additional masking operations, thereby removing a productivity-limiting step while maintaining manufacturing precision

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the drive current of NMOS devices by introducing tensile stress and simplifies the manufacturing process by eliminating the need for separate masking in PMOS regions, thereby reducing costs and process variations.

Implementation Method 1

The formation of the raised source/drains often involves epitaxially growing a silicon layer on the top surfaces of source/drain regions of NMOS devices

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

forming a silicon germanium stressor and simultaneously growing a silicon layer using an epitaxy with the p-type impurities doped in-situ to introduce tensile stress

Methodology Applied
Scientific EffectStress:

Data Source

PatentUS8889501B2Methods for forming MOS devices with raised source/drain regions
Publication Date: 2014.11.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8889501B2 patent drawing
  • US8889501B2 patent drawing
  • US8889501B2 patent drawing

AI summary

A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.