MOS Device Recess Depth Control via Sidewall Spacer Protection
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Solution Overview
Problem
In MOS devices, particularly pMOS devices, the formation of deep recesses under the gate structure leads to increased junction depth and adverse short channel effects, reducing device performance due to impurity diffusion and recess depth challenges in existing fabrication methods.
Innovation Solution
A method involving reduced recess depths in the substrate regions close to the gate structure, achieved by using a carefully controlled etching process and a silicon alloy region with a thickness greater than 30 nm, where the depth of recesses is preferably less than 10 Å, and a protective sidewall spacer to minimize junction depth and improve short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep recesses are formed under the gate structure to accommodate SiGe regions, then compressive stress is applied to improve pMOS device performance, but junction depth increases and short channel effects are adversely affected
Solution Approach 1:
The patent applies different recess depths in different regions: shallow recesses (less than 30 Å) under the gate structure to minimize junction depth and short channel effects, while maintaining sufficient recess depth in other areas to accommodate SiGe regions for stress application. This local differentiation resolves the contradiction by optimizing each region's recess depth according to its specific functional requirements.
2Ease of manufacture
If hard mask is removed using H3PO4 after epitaxially growing SiGe regions, then the fabrication process is simplified, but recess depth becomes difficult to control and exceeds 30 Å
Solution Approach 1:
The patent performs the etching process to form recesses before epitaxially growing the SiGe regions. This preliminary action allows precise control of recess depth (less than 30 Å under the gate) before the SiGe growth begins, avoiding the difficulty of controlling recess depth that occurs when etching is performed after SiGe growth and hard mask removal.
3Quantity of substance
If doped SiGe regions are formed with deep recesses, then impurity diffusion during thermal processes increases, but junction abruptness is reduced and short channel effects are adversely affected
Solution Approach 1:
The patent implements local quality control by creating shallow recesses (less than 30 Å) specifically under the gate structure where junction abruptness is critical. This localized shallow recess configuration prevents excessive impurity diffusion in the critical junction region while still allowing sufficient impurity concentration in SiGe regions elsewhere to provide the necessary compressive stress for device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device drive currents and reduces leakage currents by minimizing recess depth, thereby improving the performance of pMOS devices and maintaining compatibility with existing fabrication processes.
Implementation Method 1
a carefully controlled etching process for forming the gate structure
Implementation Method 2
Since SiGe has a greater lattice constant then silicon, SiGe regions 2 press on the channel region 8, so that a compressive stress is developed in the channel region 8
Implementation Method 3
At least one portion of the first sidewall spacer protects a surface region of the substrate close to the gate structure during the step of removing the hard mask
Data Source
AI summary
A MOS device having reduced recesses under a gate spacer and a method for forming the same are provided. The MOS device includes a gate structure overlying the substrate, a sidewall spacer on a sidewall of the gate structure, a recessed region having a recess depth of substantially less than about 30 Å underlying the sidewall spacer, and a silicon alloy region having at least a portion in the substrate and adjacent the recessed region. The silicon alloy region has a thickness of substantially greater than about 30 nm. A shallow recess region is achieved by protecting the substrate when a hard mask on the gate structure is removed. The MOS device is preferably a pMOS device.